FIR Filtering: Basic Assembly Exercise for TI TMS320C54x

Module by: Douglas L. Jones, Swaroop Appadwedula, Matthew Berry, Mark Haun, Jake Janovetz, Michael Kramer, Dima Moussa, Daniel Sachs, Brian Wade

Summary: You will work through a section of TI TMS320C54x assembly code by hand. The instructions include multiplication of fractional numbers in two's complement representation.

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Assembly Exercise

Analyze the following lines of code. Refer to Two's Complement and Fractional Arithmetic for 16-bit Processors, Addressing Modes for TI TMS320C54x, and the Mnemonic Instruction Set manual for help.

	
	1  FIR_len .set    3
	2
	3  ; Assume: 
	4  ;   BK = 3
	5  ;   AR0 = 1
	6  ;   AR2 = 1000h
	7  ;   AR3 = 1004h
	8  ;
	9  ;   FRCT = 1
	10
	11      stl     A,*AR3+%
	12      rptz    A,(FIR_len-1)
	13      mac     *AR2+0%,*AR3+0%,A

	Anything following a ";" is considered a comment.
	In this case, the comments indicate the contents of the
	auxiliary registers, BK, AR0,
	AR2, and AR3 before the execution of
	the first instruction, stl.  Note that any number
	followed by an "h" or preceded with a
	0x represents a hexadecimal value.
      

Example 1

1000h and 0x1000 both refer to the decimal number 4096.

Assume that the data memory is initialized as follows starting at location 1000h.

Figure 1: Data Memory Assignment (before execution)

After familiarizing yourself with the stl, rptz, and mac instructions, step through each line of code and record the values of the accumulator A and auxiliary registers AR2 and AR3 in the spaces provided in Figure 2. Additionally, record the value of the memory contents after all three instructions have been "executed" in the blank data memory table provided in Figure 3.

A	AR2	AR3
`00 0000 8000h`	`1000h`	`1004h`	at start of code
			after `stl` instruction
			after `rptz` instruction
			after first `mac` instruction
			after second `mac` instruction
			after third `mac` instruction

Figure 2: Execution Results

When working through the exercise, take into account that the accumulator A is a 40-bit register, and that the multiplier is in the fractional arithmetic mode. In this mode, integers on the DSP are interpreted as fractions, and the multiplier will treat them accordingly. This is done by shifting the result of the integer multiplier in the ALU left one bit. (Assume the multiplier is in fractional arithmetic mode for all exercises, unless you are told otherwise.) Therefore, multiplies performed by the ALU (via the mac instruction) produce a result that is twice what you would expect if you just multiplied the two integers together. DSP numerical representation and arithmetic are described further in Two's Complement and Fractional Arithmetic for 16-bit Processors.