FIR Filtering: Basic Assembly Exercise for TI TMS320C54x 2.19 2001/05/30 2003/07/31 09:38:21.523 GMT-5 Swaroop Appadwedula appadwed@uiuc.edu Douglas L. Jones dl-jones@uiuc.edu Michael L. Kramer kramer@ifp.uiuc.edu Dima Moussa dmoussa@uiuc.edu Brian Wade bwade@uiuc.edu Jake Janevitz jake@janevitz.com Daniel Grobe Sachs sachs@uiuc.edu Matthew J. Berry mjberry@uiuc.edu Mark A. Haun markhaun@uiuc.edu Swaroop Appadwedula appadwed@uiuc.edu Douglas L. Jones dl-jones@uiuc.edu Daniel Grobe Sachs sachs@uiuc.edu Matthew J. Berry mjberry@uiuc.edu Mark D. Butala butala@uiuc.edu Ricardo Anthony Radaelli-Sanchez ricky@alumni.rice.edu Robert L. Morrison rlmorris@uiuc.edu assembly two's-compliment fractional arithmetic hexadecimal stl mac rptz DSP You will work through a section of TI TMS320C54x assembly code by hand. The instructions include multiplication of fractional numbers in two's complement representation.

Assembly Exercise Analyze the following lines of code. Refer to Two's Complement and Fractional Arithmetic for 16-bit Processors, Addressing Modes for TI TMS320C54x, and the Mnemonic Instruction Set manual for help. Anything following a ";" is considered a comment. In this case, the comments indicate the contents of the auxiliary registers, BK, AR0, AR2, and AR3 before the execution of the first instruction, stl. Note that any number followed by an "h" or preceded with a 0x represents a hexadecimal value. 1000h and 0x1000 both refer to the decimal number 4096. Assume that the data memory is initialized as follows starting at location 1000h.

Data Memory Assignment (before execution)

After familiarizing yourself with the stl, rptz, and mac instructions, step through each line of code and record the values of the accumulator A and auxiliary registers AR2 and AR3 in the spaces provided in . Additionally, record the value of the memory contents after all three instructions have been "executed" in the blank data memory table provided in .

A AR2 AR3 00 0000 8000h 1000h 1004h at start of code after stl instruction after rptz instruction after first mac instruction after second mac instruction after third mac instruction Execution Results

When working through the exercise, take into account that the accumulator A is a 40-bit register, and that the multiplier is in the fractional arithmetic mode. In this mode, integers on the DSP are interpreted as fractions, and the multiplier will treat them accordingly. This is done by shifting the result of the integer multiplier in the ALU left one bit. (Assume the multiplier is in fractional arithmetic mode for all exercises, unless you are told otherwise.) Therefore, multiplies performed by the ALU (via the mac instruction) produce a result that is twice what you would expect if you just multiplied the two integers together. DSP numerical representation and arithmetic are described further in Two's Complement and Fractional Arithmetic for 16-bit Processors.

Data Memory Assignment (after execution)