The phase lock loop provides estimates of the phase of the incoming modulated signal. A phase ambiguity of exactly π is a common occurance in many phase lock loop (PLL) implementations.

Therefore it is possible that, θ ^ =θ+π θ ^ θ without the knowledge of the receiver. Even if there is no noise, if b=1 b 1 then b ^ =0 b ^ 0 and if b=0 b 0 then b ^ =1 b ^ 1 .

In the presence of noise, an incorrect decision due to noise may results in a correct final desicion (in binary case, when there is π phase ambiguity with the probability:

Consider a stream of bits a n ∈01 a n 0 1 and BPSK modulated signal

In differential PSK, the transmitted bits are first encoded b n = a n ⊕ b n − 1 b n a n b n − 1 with initial symbol (e.g. b 0 b 0 ) chosen without loss of generality to be either 0 or 1.

Transmitted DPSK signals

The decoder can be constructed as

If two consecutive bits are detected correctly, if b ^ n = b n b ^ n b n and b ^ n − 1 = b n − 1 b ^ n − 1 b n − 1 then

if b ^ n = b n ⊕1 b ^ n b n 1 and b ^ n − 1 = b n − 1 ⊕1 b ^ n − 1 b n − 1 1 . That is, two consecutive bits are detected incorrectly. Then, If b ^ n = b n ⊕1 b ^ n b n 1 and b ^ n − 1 = b n − 1 b ^ n − 1 b n − 1 , that is, one of two consecutive bits is detected in error. In this case there will be an error and the probability of that error for DPSK is This approximation holds if QQ is small.

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This work is licensed by Behnaam Aazhang under a Creative Commons Attribution License (CC-BY 1.0), and is an Open Educational Resource.

Last edited by Charlet Reedstrom on Sep 2, 2004 1:17 pm -0500.