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Differential Phase Shift Keying

Module by: Behnaam Aazhang

Summary: A description of differential phase shift keying, which is a method of error correcting for the common pi phase ambiguity in phase lock loops.

The phase lock loop provides estimates of the phase of the incoming modulated signal. A phase ambiguity of exactly π is a common occurance in many phase lock loop (PLL) implementations.

Therefore it is possible that, θ ^ =θ+π θ ^ θ without the knowledge of the receiver. Even if there is no noise, if b=1 b 1 then b ^ =0 b ^ 0 and if b=0 b 0 then b ^ =1 b ^ 1 .

In the presence of noise, an incorrect decision due to noise may results in a correct final desicion (in binary case, when there is π phase ambiguity with the probability:

P e ¯ =1-Q2 E s N 0 P e ¯ 1 Q 2 E s N 0 (1)

Consider a stream of bits a n ∈01 a n 0 1 and BPSK modulated signal

∑n-1 a n A P T t-nTcos2π f c t+θ n n -1 a n A P T t n T 2 f c t θ (2)

In differential PSK, the transmitted bits are first encoded b n = a n ⊕ b n − 1 b n a n b n − 1 with initial symbol (e.g. b 0 b 0 ) chosen without loss of generality to be either 0 or 1.

Transmitted DPSK signals

∑n-1 b n A P T t-nTcos2π f c t+θ n n -1 b n A P T t n T 2 f c t θ (3)

The decoder can be constructed as

b n − 1 ⊕ b n = b n − 1 ⊕ a n ⊕ b n − 1 =0⊕ a n = a n b n − 1 b n b n − 1 a n b n − 1 0 a n a n (4)

If two consecutive bits are detected correctly, if b ^ n = b n b ^ n b n and b ^ n − 1 = b n − 1 b ^ n − 1 b n − 1 then

a ^ n = b ^ n ⊕ b ^ n − 1 = b n ⊕ b n − 1 = a n ⊕ b n − 1 ⊕ b n − 1 = a n a ^ n b ^ n b ^ n − 1 b n b n − 1 a n b n − 1 b n − 1 a n (5)
if b ^ n = b n ⊕1 b ^ n b n 1 and b ^ n − 1 = b n − 1 ⊕1 b ^ n − 1 b n − 1 1 . That is, two consecutive bits are detected incorrectly. Then,
a ^ n = b ^ n ⊕ b ^ n − 1 = b n ⊕1⊕ b n − 1 ⊕1= b n ⊕ b n − 1 ⊕1⊕1= b n ⊕ b n − 1 ⊕0= b n ⊕ b n − 1 = a n a ^ n b ^ n b ^ n − 1 b n 1 b n − 1 1 b n b n − 1 1 1 b n b n − 1 0 b n b n − 1 a n (6)
If b ^ n = b n ⊕1 b ^ n b n 1 and b ^ n − 1 = b n − 1 b ^ n − 1 b n − 1 , that is, one of two consecutive bits is detected in error. In this case there will be an error and the probability of that error for DPSK is
P ¯ e =Pr a ^ n ≠ a n =Pr b ^ n = b n b ^ n − 1 ≠ b n − 1 +Pr b ^ n ≠ b n b ^ n − 1 = b n − 1 =2Q2 E s N 0 1-Q2 E s N 0 ≈2Q2 E s N 0 P ¯ e a ^ n a n b ^ n b n b ^ n − 1 b n − 1 b ^ n b n b ^ n − 1 b n − 1 2 Q 2 E s N 0 1 Q 2 E s N 0 2 Q 2 E s N 0 (7)
This approximation holds if QQ is small.

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