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Basic MOS Structure

Module by: Bill Wilson. E-mail the author

Summary: Discussing the basic MOS structure.

Figure 1: Formation of the MOS structure
Figure 1 (4.02.png)

Figure 1 shows the steps necessary to make the MOS structure. It will help us in our understanding if we now rotate our picture so that it is pointing sideways in our next few drawings. (Also, we will forget about the two n-regions for awhile, and pick them back up later when we rotate the structure right side up again.) Figure 2 shows the rotated structure. Note that in the p-silicon we have positively charged mobile holes, and negatively charged, fixed acceptors. Because we will need it later, we have also shown the band diagram for the semiconductor below the sketch of the device. Note that since the substrate is p-type, the Fermi level is located down close to the valance band.

Figure 2: Basic MOS structure
Figure 2 (4.03.png)

Let us now place a potential between the gate and the silicon substrate. Suppose we make the gate negative with respect to the substrate. Since the substrate is p-type, it has a lot of mobile, positively charged holes in it. Some of them will be attracted to the negative charge on the gate, and move over to the surface of the substrate. This is also reflected in the band diagram below the sketch of the structure. Remember that the density of holes is exponentially proportional to how close the Fermi level is to the valence band edge. We see that the band diagram has been bent up slightly near the surface to reflect the extra holes which have accumulated there.

Figure 3: Applying a negative gate voltage
Figure 3 (4.04.png)

An electric field will develop between the positive holes and the negative gate charge. Note that the gate and the substrate form a kind of parallel plate capacitor, with the oxide acting as the insulating layer in-between them. The oxide is quite thin compared to the area of the device, and so it is quite appropriate to assume that the electric field inside the oxide is a uniform one. (We will ignore fringing at the edges.) The integral of the electric field is just the applied gate voltage Vg Vg . If the oxide has a thickness xox xox then since Eox Eox is uniform, it is given by

E ox = V g x ox E ox V g x ox
(1)

If we focus in on a small part of the gate, we can make a little "pill" box which extends from somewhere in the oxide, across the oxide/gate interface and ends up inside the gate material someplace. The pill-box will have an area Δs Δ s . Now we will invoke Gauss' law which we reviewed earlier. Gauss' law simply says that the surface integral over a closed surface of the displacement vector DD (which is, of course, just εε times EE) is equal to the total charge enclosed by that surface. We will assume that there is a surface charge density Q g Q g ( Coulombscm2 Coulombs cm 2 ) on the surface of the gate electrode. The integral form of Gauss' Law is just:

ε ox Ed S = Q encl S ε ox E Q encl
(2)

Figure 4: Finding the surface charge density
Figure 4 (4.05.png)

Note that we have used ε ox E ε ox E in place of DD. In this particular set-up the integral is easy to perform, since the electric field is uniform, and only pointing in through one surface - it terminates on the negative surface charge inside the pill-box. The charge enclosed in the pill box is just ( Q g Δs) Q g Δ s , and so we have (keeping in mind that the surface integral of a vector pointing into the surface is negative)

ε ox Ed S =( ε ox E ox Δs)=( Q g Δs) S ε ox E ε ox E ox Δ s Q g Δ s
(3)
or
ε ox E ox = Q g ε ox E ox Q g
(4)

Now, we can use Equation 1 to get

ε ox V g x ox = Q g ε ox V g x ox Q g
(5)
or
Q g V g = ε ox x ox c ox Q g V g ε ox x ox c ox
(6)

The quantity cox cox is called the oxide capacitance. It has units of Faradscm2 Farads cm 2 , so it is really a capacitance per unit area of the oxide. The dielectric constant of silicon dioxide, εox εox , is about 3.3×10-13F/cm 3.3-13 F/cm . A typical oxide thickness might be 250 Å (or 2.5×10-6cm 2.5-6 cm ). In this case, cox cox would be about 1.30×10-7Fcm2 1.30-7 F cm 2 . (The units we are using here, while they might seem a little arbitrary and confusing, are the ones most commonly used in the semiconductor business. You will get used to them in a short while.)

The most useful form of Equation 6 is when it is turned around:

Q g = c ox V g Q g c ox V g
(7)
as it gives us a way to find the charge on the gate in terms of the gate potential. We will use this equation later in our development of how the MOS transistor really works.

It turns out we have not done anything very useful by apply a negative voltage to the gate. We have drawn more holes there in what is called an accumulation layer, but that is not helping us in our effort to create a layer of electrons in the MOSFET which could electrically connect the two n-regions together.

Let's turn the battery around and apply a positive voltage to the gate. (Actually, let's take the battery out of the sketch for now, and just let Vg Vg be a positive value, relative to the substrate which will tie to ground.) Making Vg Vg positive puts positive Qg Qg on the gate. The positive charge pushes the holes away from the region under the gate and uncovers some of the negatively-charged fixed acceptors. Now the electric field points the other way, and goes from the positive gate charge, terminating on the negative acceptor charge within the silicon.

Figure 5: Increasing the voltage extends the depletion region further into the device
Figure 5 (4.06.png)

The electric field now extends into the semiconductor. We know from our experience with the p-n junction that when there is an electric field, there is a shift in potential, which is represented in the band diagram by bending the bands. Bending the bands down (as we should moving towards positive charge) causes the valence band to pull away from the Fermi level near the surface of the semiconductor. If you remember the expression we had for the density of holes in terms of Ev Ev and Ef Ef (electron and hole density equations) it is easy to see that indeed

p= N v e E f E v kT p N v E f E v k T
(8)
there is a depletion region (region with almost no holes) near the region under the gate. (Once E f E v E f E v gets large with respect to kT k T , the negative exponent causes p0 p 0 .)

Figure 6: Threshold, Ef Ef is getting close to Ec Ec
Figure 6 (4.07.png)

The electric field extends further into the semiconductor, as more negative charge is uncovered and the bands bend further down. But now we have to recall the electron density equation, which tells us how many electrons we have

n= N c e E c E f kT n N c E c E f k T
(9)

A glance at Figure 6 above reveals that with this much band bending, Ec Ec the conduction band edge, and Ef Ef the Fermi level are starting to get close to one another (at least compared to kT k T ), which means that nn, the electron concentration, should soon start to become significant. In the situation represented by Figure 6, we say we are at threshold, and the gate voltage at this point is called the threshold voltage, VT VT .

Now, let's increase Vg Vg above VT VT . Here's the sketch in Figure 7.

Figure 7: Inversion - Electrons form an inversion layer under the gate
Figure 7 (4.08.png)

Even though we have increased Vg Vg beyond the threshold voltage, VT VT , and more positive charge appears on the gate, the depletion region no longer moves back into the substrate. Instead electrons start to appear under the gate region, and the additional electric field lines terminate on these new electrons, instead of on additional acceptors. We have created an inversion layer of electrons under the gate, and it is this layer of electrons which we can use to connect the two n-type regions in our initial device.

Where did these electrons come from? We do not have any donors in this material, so they can not come from there. The only place from which electrons could be found would be through thermal generation. Remember, in a semiconductor, there are always a few electron hole pairs being generated by thermal excitation at any given time. Electrons that get created in the depletion region are caught by the electric field and are swept over to the edge by the gate. I have tried to suggest this with the electron generation event shown in the band diagram in the figure. In a real MOS device, we have the two n-regions, and it is easy for electrons from one or both to "fall" into the potential well under the gate, and create the inversion layer of electrons.

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