There are other kinds of MOSFET's besides the one we have studied so far. Strictly speaking, what we have seen up to now is called an n-channel enhancement mode MOSFET. It turns out that you can build a MOSFET which looks just like a previous figure, except that by putting some additional impurities under the gate region, we can arrange it so that there is a channel formed, even with V g =0 V g 0 . The transistor now has a negative VT VT . The process by which the additional impurities are added is called a VT VT adjust.

A MOSFET with a negative VT VT can be expected to have I d − V ds I d V ds curves similar to those for a positive VT VT device, except for one thing. For V gs =0 V gs 0 , the device is already turned on, and so we get a usual MOSFET-type curve. Positive gate voltage turns it on even more, while negative Vgs Vgs tends to reduce the drain current. It takes a negative gate voltage to turn the thing off. Figure 1 shows comparative characteristic curves for an enhancement and depletion mode devices.

For an enhancement mode transistor, you have to get V g > V T V g V T (-1 Volt in this example) to enhance the conductivity or channel to make it conduct. For a depletion mode device, a gate voltage Vgs of 0, still finds the device conducting. You have to put some negative voltage on the gate to deplete the channel, in order to turn it off. We now have a depletion mode n-channel MOSFET.

How would we use a depletion mode device in an inverter gate? The answer is fairly straight-forward. In the schematic in Figure 2, we indicate a depletion mode MOSFET by adding a second line, under the gate, to suggest that a channel already exists in the device, even with no Vg Vg . Note that the gate of the depletion mode transistor (also sometimes called the pull up transistor) is connected to its source, so, in fact, Vgs Vgs does equal 0 for this device. The input transistor (or the pull down transistor) is just an enhancement mode MOSFET like we had before. It is not hard to choose appropriate WW and LL so that Idsat Idsat for the pull up transistor is on the order of the 500 μA that we need to get our 1 ns rise time on the capacitive load.

In order to get the transfer characteristic for this circuit, we first note that

where Vsde Vsde is the source-drain voltage for the pull-down, or enhancement transistor, and Vsdd Vsdd , is the source-drain voltage for the depletion-mode transistor. If we want to plot the load-line for the pull-down transistor that is created by the pull-up or depletion mode transistor, we should take its V gs =0 V gs 0 characteristic curve, shift it over by an amount Vdd Vdd , and then reverse its polarity. When we do this we get the following shown in Figure 3. Noting the intersection points of the load line and the characteristic curves allows us the opportunity for drawing the transfer characteristic. This is a better looking curve. It is symmetric around the mid-voltage point, and gets closer to zero for its output "low" condition. The transition from "high" to "low" is also somewhat more abrupt, which is advantageous. Can you figure out why?

Well, we solved one problem. At least we have a pull up structure that we can manufacture. It turns out not to be too hard to build an enhancement MOSFET that has an equivalent resistance in the range we need without taking up too much chip area. We have not solved the other problem however. We are still looking at a huge current draw for large circuits. Since on average, half of the inverter gates will be "on" in a logic circuit, we still have a large current sink to ground. This is something that would be completely prohibitive in a modern-day VLSI integrated circuit.

Fortunately, we have not run out of options for MOS structures yet.

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This work is licensed by Bill Wilson under a Creative Commons Attribution License (CC-BY 1.0), and is an Open Educational Resource.

Last edited by Raymond Wagner on Aug 14, 2007 1:18 pm GMT-5.