TMS320C6000 DSP ARCHITECTURE

The TMS320C62x TM TMS320C62x TM and TMS320C67x TM TMS320C67x TM devices are based on VelociTI TM VelociTI TM , an advanced Very Long Instruction Word (VLIW) architecture. This highly parallel and deterministic architecture emphasizes software-based flexibility and maximum code performance through the industry's most efficient C compiler and the industry's first Assembly Optimizer. For designers, the direct translation is faster time to market with highly integrated and differentiated products.

Figure 1

The eight functional units of the C6000 TM C6000 TM DSP core, including two multipliers and six arithmetic units, are highly orthogonal, providing the compiler and Assembly Optimizer with many execution resources. Eight 32-bit RISC-like instructions are fetched by the CPU each cycle. VelociTI's instruction packing features allow these eight instructions to be executed in parallel, in serial, or in parallel/serial combinations. This optimized scheme enables significant reductions in code size, number of program fetches and power consumption.

The C67x TM C67x TM DSP instruction set has added floating-point capability to six of the eight functional units available on the C6000 DSP architecture, making it a superset of the C62x TM C62x TM fixed-point instruction set. Because of this, all C62x DSP instructions will run unmodified on the C67x CPU.

Highlights of the TMS320C64x DSP Architecture

The C64x TM C64x TM DSP generation features TI's VelociTI.2 TM VelociTI.2 TM VLIW architecture extensions that include support for packed data processing and special purpose instructions to accelerate broadband infrastructure and imaging applications. The C64x generation is scalable to clock speeds up to 1.1 GHz and can incorporate multiple memory, peripheral and voltage combinations to address a wide range of high performance applications.

Figure 2

C64x TM C64x TM DSP architechture highlights include: