Summary: The phase-locked loop (PLL) is a critical component in coherent communications receivers that is responsible for locking on to the carrier of a received modulated signal. A PLL adjusts the phase of a numerically-controlled oscillator to match that of the received signal. You will simulate a carrier recovery sub-system in MATLAB and then implement the sub-system on the DSP.
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After gaining a theoretical understanding of the carrier recovery sub-system of a digital receiver, you will simulate the sub-system in MATLAB and implement it on the DSP. The sub-system described is specifically tailored to a non-modulated carrier. A complete implementation will require modifications to the design presented.
The phase-locked loop (PLL) is a
critical component in coherent communications receivers that
is responsible for locking on to the carrier of a received
modulated signal. Ideally, the transmitted carrier frequency
is known exactly and we need only to know its phase to
demodulate correctly. However, due to imperfections at the
transmitter, the actual carrier frequency may be slightly
different from the expected frequency. For example, in the
QPSK transmitter of Digital
Transmitter: Introduction to Quadrature Phase-Shift
Keying, if the digital carrier frequency is
This difference between the expected and actual carrier frequencies can be modeled as a time-varying phase. Provided that the frequency mismatch is small relative to the carrier frequency, the feedback control of an appropriately calibrated PLL can track this time-varying phase, thereby locking on to both the correct frequency and the correct phase.
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In a complete coherent receiver implementation, carrier recovery is required since the receiver typically does not know the exact phase and frequency of the transmitted carrier. In an analog system this recovery is often implemented with a voltage-controlled oscillator (VCO) that allows for precise adjustment of the carrier frequency based on the output of a phase-detecting circuit.
In our digital application, this adjustment is performed with a numerically-controlled oscillator (NCO) (see Figure 1). A simple scheme for implementing an NCO is based on the following re-expression of the carrier sinusoid:
The goal of the PLL is to maintain a demodulating sine and
cosine that match the incoming carrier. Suppose
The estimated phase mismatch estimate is fed to the NCO via a loop filter, often a simple low-pass filter. For this exercise you can use a one-tap IIR filter,
It is suggested that you start by choosing
Simulate the PLL system shown in Figure 1 using MATLAB. As with the DLL simulation, you will have to simulate the PLL on a sample-by-sample basis.
Use Equation 3 to implement your NCO in MATLAB.
However, to ensure that the phase term does not grow to
infinity, you should use addition modulo
Figure 2 illustrates how the proposed PLL will
behave when given a modulated BPSK waveform. In this case the
transmitted carrier frequency was set to
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Note that an amplitude transition in the BPSK waveform is
equivalent to a phase shift of the carrier by
As you begin to implement your PLL on the DSP, it is highly recommended that you implement and test your NCO block first before completing the rest of your phase-locked loop.
Your NCO must be able to produce a sinusoid with
continuously variable frequency. Computing values of
Suppose a sine table stores
You may simplify the interpolation problem by using "lower-neighbor" interpolation, i.e., by using the integer part of your pointer. Note that the full-precision, non-integer pointer must be maintained in memory so that the fractional part is allowed to accumulate and carry over into the integer part; otherwise, your phase will not be accurate over long periods. For a long enough sine table, this approximation will adjust the NCO frequency with sufficient precision.4
Maintaining a non-integer pointer is more difficult. In
earlier exercises, you have used the auxiliary registers
(ARx) to manage pointers with integer
increments. The auxiliary registers are not suited for the
non-integer pointers needed in this exercise, however, so
another method is required. One possibility is to perform
addition in the accumulator with a modified decimal point.
For example, with
ARx register. The
auxiliary register now points to the correct sample in the
sine table.
As an example, for a nominal carrier frequency
You may want to refer to Proakis and Blahut. These references may help you think about the following questions:
"Doug course at UIUC using the TI C54x DSP has been adopted by many EE, CE and CS depts Worldwide "