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Digital Transmitter: Optimization Exercise with QPSK on TI TMS320C54x (ECE 320 specific)

Module by: Mark Butala. E-mail the author

Summary: (Blank Abstract)


You will implement the complete system shown in Digital Transmitter: Introduction to Quadrature Phase-Shift Keying. Then you will optimize the system for execution time. The optimization process will probably be much easier if you plan for optimization before you begin any programming.

PN generator

Once you have planned your program strategy, implement the PN generator from Digital Transmitter: Introduction to Quadrature Phase-Shift Keying and verify that it is working. You may wish to refer to the description of assembly instructions for logical operations in Section 2-2 of the Mnemonic Instruction Set [link] reference. Initialize the shift register to one.


For your transmitter implementation, use the signal constellation shown in Digital Transmitter: Introduction to Quadrature Phase-Shift Keying, a digital carrier frequency ω c ω c of π2 2 and a digital symbol period of T symb =16 T symb 16 samples.

Viewing the transmitted signal on the oscilloscope may help you determine whether your code works properly, but you should check it more carefully by setting breakpoints in Code Composer and using the Memory option from the View menu to view the contents of memory. A vector signal analyzer (VSA) provides another method of testing, which is described in Vector Signal Analyzer: Testing a QPSK Transmitter.


One objective of this exercise is to teach optimization and efficient code techniques. For this reason, your performance will be judged primarily on the total execution time of your system. Note that by execution time we mean cycle count, not the number of instructions in your program. Remember that several of the TI TMS320C54xx instructions take more than one cycle. The multicycle instructions are primarily the multi-word instructions, including instructions that take immediates, like stm, and instructions using direct addressing of memory (such as ld *(temp),A). Branch and repeat statements also require several cycles to execute. The Mnemonic Instruction Set [link] reference will tell you how many cycles required for each instruction; make sure you look at the cycle count for the syntax you are using. It is also possible to use the debugger to determine the number of cycles used by your code.

You will be graded based on the number of cycles used between the return from one WAITDATA call and the arrival at the next WAITDATA call. If the number of cycles between one WAITDATA and the next is variable, the maximum possible number of cycles will be used. You must use the core.asm file as provided; this file may not be modified. You explicitly may not change the number of samples read and written by each WAITDATA call! We reserve the right to test your code by substituting the test vector core file.


This is a two week lab. Your prelab is due a week after the quiz for Lab 4 and the quizzing for Lab 5 occurs two weeks after the quiz for Lab 4.

Grading for this lab will be a bit different from past labs:

  • 1 point: Prelab.
  • 2 points: Working code, implemented from scratch in assembly and/or C.
  • 5 points: Optimization. These points will be assigned based on your cycle counts and the optimizations you have made.
  • 2 points: Oral quiz.

Pizza Competition

The student or students with the fastest code (as defined by the criteria in Optimization) will enjoy free pizza at Papa Del's in the company of Professor Jones and the TAs.

Your final assembly and/or C source code for the pizza competition must be emailed to no later than 11:59 PM on Friday, October 18. However, you optimization grade will be assigned based on the code turned in during your assigned lab section and is subject to the usual policies for late code.

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