Using 2's compliment integer representation, we can implement both addition and subtraction by usual binary addition (with special care for the sign bit). However, the integers are not convenient to handle to implement common DSP algorithms. For example, if we multiply two 8-bit words together, we need 16 bits to store the result. The number of required word length increases without bound as we multiply numbers together. Although not impossible, it is complicated to handle this increase in word length using integer arithmetic.

Instead, by using fractional numbers between -1 and 1, we can easily handle the results of multiplication because the product of two numbers is always in the same range.

In the 2's complement fractional representation, an NN bit binary word can represent equally spaced 2N 2 N numbers from −2N−12N−1=-1 2 N 1 2 N 1 -1 to 2N−1−12N−1=1−2−(N−1) 2 N 1 1 2 N 1 1 2 N 1 . For example, we interpret an 8-bit binary word b_7b_6b_5b_4b_3b_2b_1b_0 as a fractional number

This representation is also called Q-format representation. We can think of having an implied binary point right after the MSB. If we have an N-bit binary word with MSB as the sign bit, we have N-1 bits to represent the fractional magnitude. We say the number has Q-(N-1) format representation. In 32bit DSP processor such as TI TMS320C62x, it is easiest to handle Q-15 format numbers represented by each 16-bit binary word, because the product of two Q-15 numbers is a Q-30 number that can still be stored in a 32-bit register. The programmer needs to keep track of the implied binary point when multiplying the Q format numbers.