Implementation of Q-15 arithmetic on TI TMS320C62x 2.0 2002/10/15 2002/10/15 Hyeokho Choi choi@ece.rice.edu Hyeokho Choi choi@ece.rice.edu Q-15 TMS320C62x This explains how to implenet Q-15 multiplication on TMS320C62x CPU.

Implementation of Q-15 multiplication on TMS320C62x

Assembly language implementation When A0 and A1 contain two 16-bit numbers in the Q-15 format, we can perform the multiplications using MPY followed by a right shift. Rather than throwing away the 15 LSBs of the multiplication result by shifting, you can round up the result by adding 0x4000 before shifting.

C language implementation Let's suppose we have two 16-bit numbers in Q-15 format, stored in variable x and y as follows: The product of x and y can be computed and stored in Q-15 format as follows: > 15; ]]> The result of x*y is a 32-bit word with 2 sign bits. Right shifting it by 15 bits ignores the last 15 bits, and storing the shifted result in z that is a short variable (16 bit) removes the extended sign bit by taking only lower 16 bits.