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Implementation of Q-15 arithmetic on TI TMS320C62x

Module by: Hyeokho Choi. E-mail the author

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Summary: This explains how to implenet Q-15 multiplication on TMS320C62x CPU.

Implementation of Q-15 multiplication on TMS320C62x

Assembly language implementation

When A0 and A1 contain two 16-bit numbers in the Q-15 format, we can perform the multiplications using MPY followed by a right shift. 


	    
	    MPY	.M1	A0,A1,A2
	    NOP
	    SHR	.S1	A2,15,A2	;lower 16 bit contains result
	    ;in Q-15 format

Rather than throwing away the 15 LSBs of the multiplication result by shifting, you can round up the result by adding 0x4000 before shifting. 


	    
	    MPY	.M1	A0,A1,A2
	    NOP
	    ADDK	.S1	4000h,A6
	    SHR	.S1	A2,15,A2	;lower 16 bit contains result
	    ;in Q-15 format

C language implementation

Let's suppose we have two 16-bit numbers in Q-15 format, stored in variable x and y as follows: 


	    
	    short x = 0x0011;     /*   0.000518799 in decimal */
	    short y = 0xfe12;     /*  -0.015075684 in decimal */
	    short z;              /* variable to store x*y */

The product of x and y can be computed and stored in Q-15 format as follows: 


	    
	    z = (x * y) >> 15;

The result of x*y is a 32-bit word with 2 sign bits. Right shifting it by 15 bits ignores the last 15 bits, and storing the shifted result in z that is a short variable (16 bit) removes the extended sign bit by taking only lower 16 bits.

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