Typical Assembly Operations

	      100h  fe54  7834h
	      104h  3459  f34dh
	      108h  2ef5  7ee4h
	      10ch  2345  6789h
	      110h  ffff  eeddh
	      114h  3456  787eh
	      118h  3f4d  7ab3h
	    

	   1     LDW   .D1    *A10, A1
	   2     MV    .D1    A1,A2
	  

	    1     LDW    .D1    *A10, A1
	    2     NOP
	    3     NOP
	    4     NOP
	    5     NOP
	    6     MV     .D1    A1,A2
	  

	    1     LDW    .D1    *A10, A1
	    2     NOP  4
	    3     MV     .D1    A1,A2
	  

	1     LDW    .D1    *A10, A4
	2     ADD    .D1    A1,A2,A3
	

	  1     LDW    .D1    *A10++[A2], A9
	  2     MV     .L1    A10, A8
	  3     MV     .L1    A1, A10
	  4     MV     .L1    A1, A2
	  5     ...
	

	  1    [B0]    B     .L1    A0
	

	  1    [!B0]    B     .L1    A0
	

Useful assembler directives

Other than the CPU instruction set, there are special commands to the assembler that direct the assembler to do various jobs when assembling the code. You should learn about some of these assembler directives to be able to write an assembly program. There are useful assembler directives you can use to let the assembler know various settings, such as .set, .macro, .endm, .ref, .align, .word, .byte .include.,

The .set directive defines a symbolic name. For example, you can have

	1    count    .set    40
      

Then, the assembler replaces each occurrence of count with 40.

You have already seen how the .ref directive is used to declare symbolic names defined in another file. It is similar to the extern declaration in C.

The .space directive reserves a memory space with specified number of bytes. For example, you can have

	1    buffer    .space    128
      

to define a buffer of size 128 bytes. The symbol buffer has the address of the first byte reserved by .space. The .bes directive is similar to .space, but the label has the address of the last byte reserved.

To put a constant value in the memory, you can use .byte, .word, etc. If you have

	1    const1    .word    0x1234
      

the assembler places the word constant 0x1234 at a memory location and const1 has the address of the memory location. .byte etc. works similarly.

Sometimes you need to place your data or code at a specific memory address boundaries such as word, halfword, etc. You can use the .align directive to do this. For example, if you have

	1               .align    4
	2     buffer    .space    128
	3               ...
      

Then, the first address of the reserved 128 bytes is at the word boundary in memory, that is the 2 LSBs of the address (in binary) are 0. Similarly, for half-word alignment, you should have .align directive to do this. For example, if you have

	1               .align    2
	2     buffer    .space    128
	3               ...
      

The .include directive is used to read the source lines from another file. If you have

	1               .include    ``other.asm''
      

will input the lines in other.asm at this location. This is useful when working with multiple files. Instead of making a project having multiple files, you can simply include these different files in one file.

Other assembler directives include .end, etc. You will learn about the macro directives .macro, .endm later .

How do you write comments in your assembly program? Anything that follows ; is considered as a comment and ignored by the assembler. For example,

	1     ; this is a comment
	2             ADD     .L1     A1,A2,A3      ;add a1 and a2
      

Assigning functional units

Each instruction has particular functional units that can execute it. For a complete list of the instructions that can be executed in each functional unit, see Table 3-2 in the instruction set manual. Note that some instructions can be executed by several different functional units.

(Reference) shows how data and addresses can be transfered between the registers, functional units and the external memory. If you observe carefully, the destination path (marked as dst) going out of the .L1, .S1, .M1 and D1 units are connected to the register file A.

Therefore if you know the instruction and the destination register, you should be able to assign the functional unit to it.

If you look at (Reference) again, each functional unit must receive one of the source data from the corresponding register file. For example, look at the following assembly instruction:

	1     ADD   .L1    A0,B0,A1
      

The .L1 unit gets data from A0 (this is natural) and B0 (this is not) and stores the result in A1 (this is a must). The data path through which the content of B0 is conveyed to the .L1 unit is called 1X cross path. When this happens, we add x to the functional unit to designate the cross path:

	1    ADD    .L1x    A0,B0,A1
      

Similarly the data path from register file B to the .M2, .S2 and .L2 units are called 2X cross path.

In fact, when you write an assembly program, you can omit the functional unit assignment altogether. The assembler figures out the available functional units and properly assigns them. However, manually assigned functional units help you to figure out where the actual execution takes place and how the data move around between register files and functional units. This is particularly useful when you put multiple instructions in parallel. We will learn about the parallel instructions later on.

Writing the inner product program

Now you should know enough about C62x assembly to implement the inner product algorithm to compute y=∑n=110 a n × x n y n 1 10 a n x n

	    a[] = { 1, 2, 3, 4, 5, 6, 7, 8, 9, a }
	    x[] = { f, e, d, c, b, a, 9, 8, 7, 6 }
	  

Pipeline, Delay slots and Parallel instructions

When an instruction is executed, it takes several steps, which are fetching, decoding, and execution. If these steps are done one at a time for each instruction, the CPU resources are not fully utilized. To increase the throughput, CPUs are designed to be pipelined, meaning that the foregoing steps are carried out at the same time.

On the C6x processor, the instruction fetch consists of 4 phases; generate fetch address (F1), send address to memory (F2), wait for data (F3), and read opcode from memory (F4). Decoding consists of 2 phases; dispatching to functional units (D1) and decoding (D2). The execution step may consist of up to 6 phases (E1 to E6) depending on the instructions. For example, the multiply (MPY) instructions has 1 delay resulting in 2 execution phases. Similarly, load (LDx) and branch (B) instructions have 4 and 5 delays respectively.

When the outcome of an instruction is used by the next instruction, an appropriate number of NOPs (no operation or delay) must be added after multiply (one NOP), load (four NOPs, or NOP 4), and branch (five NOPs, or NOP 5) instructions in order to allow the pipeline to operate properly. Otherwise, before the outcome of the current instruction is available (which is to be used by the next instruction), the next instructions are executed by the pipeline, generating undesired results. The following code is an example of pipelined code with NOPs inserted:

	 1             MVK    40,A2
	 2     loop:   LDH    *A5++,A0
	 3             LDH    *A6++,A1
	 4             NOP    4
	 5             MPY    A0,A1,A3
	 6             NOP
	 7             ADD    A3,A4,A4
	 8             SUB    A2,1,A2
	 9     [A2]    B      loop
	10             NOP    5
	11             STH    A4,*A7
      

In line 4, we need 4 NOPs because the A1 is loaded by the LDH instruction in line 3 with 4 delays. After 4 delays, the value of A1 is available to be used in the MPY A0,A1,A3 in line 5. Similarly, we need 5 delays after the [A2] B loop instruction in line 9 to prevent the execution of STH A4,*A7 before branching occurs.

The C6x Very Large Instruction Word (VLIW) architecture, several instructions are captured and processed simultaneously. This is referred to as a Fetch Packet (FP). This Fetch Packet allows C6x to fetch eight instructions simultaneously from on-chip memory. Among the 8 instructions fetched at the same time, multiple of them can be executed at the same time if they do not use same CPU resources at the same time. Because the CPU has 8 separate functional units, maximum 8 instructions can be executed in parallel, although the type of parallel instructions are limited because they must not conflict each other in using CPU resources. In assembly listing, parallel instructions are indicated by double pipe symbols (||). When writing assembly code, by designing code to maximize parallel execution of instructions (through proper functional unit assignments, etc.) the execution cycle of the code can be reduced.

Parallel instructions and constraints

We have seen that C62x CPU has 8 functional units. Each assembly instruction is executed in one of these 8 functional units, and it takes exactly one clock cycle for the execution. Then, while one instruction is being executed in one of the functional units, what are other 7 functional units doing? Can other functional units execute other instructions at the same time?

The answer is YES. Thus, the CPU can execute maximum 8 instructions in each clock cycle. The instructions executed in the same clock cycle are called parallel instructions. Then, what instructions can be executed in parallel? A short answer is: as far as the parallel instructions do not use the same resource of the CPU, they can be put in parallel. For example, the following two instructions do not use the same CPU resource and they can be executed in parallel.

	1           ADD    .L1    A0,A1,A2
	2    ||     ADD    .L2    B0,B1,B2
      

	    1          ADD     .L1x    A0,B1,A2
	    2   ||     MPY     .M1x    A5,B0,A3
	  

	    1          LDW     .D2     *B0, A1
	  

	    1          LDW     .D1     *A0, A1
	    2   ||     STW     .D2     A2, *B0
	  

	    1          ADD     .L1     A1, A1, A2
	    2   ||     MPY     .M1     A1, A1, A3
	    3   ||     SUB     .D1     A1, A4, A5
	  

	    1	       ADD     .L1     A1, A1, A2
	    2   ||     MPY     .M1     A1, A1, A2
	  

	    1          MPY     .M1     A1, A1, A2
	    2          ADD     .L1     A3, A4, A2
	  

Ad-Hoc software pipelining

At this point, you might have wondered why the C62x CPU allows parallel instructions and generate so much headache with the resource constraints, especially with the instructions with delay slots. And, why not just make the MPY instruction take 2 clock cycles to execute so that we can always use the multiplied result after issuing it?

The reason is that by executing instructions in parallel, we can reduce the total execution time of the program. A well-written assembly program executes as many instructions as possible in each clock cycle to implement the desired algorithm.

The reason for allowing delay slots is that although it takes 2 clock cycles for an MPY instruction generate the result, we can execute another instruction while waiting for the result. This way, you can reduce the clock cycles wasted while waiting for the result from slow instructions, thus increasing the overall execution speed.

However, how can we put instructions in parallel? Although there's a systematic way of doing it (we will learn a bit later), at this point you can try to restructure your assembly code to execute as many instructions as possible in parallel. And, you should try to execute other instructions in the delay slots of those instructions such as MPY, LDW, etc., instead of inserting NOPs to wait the instructions produce the results.