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<document xmlns="http://cnx.rice.edu/cnxml" xmlns:md="http://cnx.rice.edu/mdml/0.4" xmlns:m="http://www.w3.org/1998/Math/MathML" xmlns:bib="http://bibtexml.sf.net/" id="new58">
  <name>Integrated Circuit Manufacturing: Bird's Eye View</name>
  <metadata>
  <md:version>1.2</md:version>
  <md:created>2003/06/20</md:created>
  <md:revised>2003/06/23 10:33:59.633 GMT-5</md:revised>
  <md:authorlist>
    <md:author id="wlw">
      <md:firstname>Bill</md:firstname>
      
      <md:surname>Wilson</md:surname>
      <md:email>wlw@rice.edu</md:email>
    </md:author>
  </md:authorlist>

  <md:maintainerlist>
    <md:maintainer id="wlw">
      <md:firstname>Bill</md:firstname>
      
      <md:surname>Wilson</md:surname>
      <md:email>wlw@rice.edu</md:email>
    </md:maintainer>
    <md:maintainer id="lizzardg">
      <md:firstname>Elizabeth</md:firstname>
      
      <md:surname>Gregory</md:surname>
      <md:email>lizzardg@rice.edu</md:email>
    </md:maintainer>
    <md:maintainer id="jsilv">
      <md:firstname>Jeffrey</md:firstname>
      
      <md:surname>Silverman</md:surname>
      <md:email>jsilv@rice.edu</md:email>
    </md:maintainer>
  </md:maintainerlist>
  
  <md:keywordlist>
    <md:keyword>circuit</md:keyword>
    <md:keyword>integrated</md:keyword>
    <md:keyword>manufacturing</md:keyword>
    <md:keyword>n-tank</md:keyword>
    <md:keyword>field</md:keyword>
    <md:keyword>oxide</md:keyword>
    <md:keyword>FOX</md:keyword>
    <md:keyword>metallization</md:keyword>
  </md:keywordlist>

  <md:abstract>This document provides a bird's eye view of Integrated Circuit manufacturing.  It steps through the process of manufacturing an IC, from the n-tank to patterning the metallization.</md:abstract>
</metadata>

  <content>
    <para id="para1">It will no doubt be helpful if we also take a
      plane or "bird's eye" view of what this circuit looks like as
      well. There are, in fact, some interesting things we can gain by
      looking at some of them.
    </para>

    <para id="para2"> We have been looking at the development of the
      circuit from a cross-sectional point of view, watching the
      formation of the various levels which make up the finished CMOS
      inverter. This is, in fact, not the way a circuit designer looks
      at things. A circuit designer sees things from above, and only
      worries about the placement of transistors, and how they will be
      connected together. In fact, the only factor in the actual
      design of the layout engineer has any choice on is the
      transistor width, W. All other parameters are decided upon
      beforehand by the process engineer. So what does the layout
      engineer see? We start with the n- implant to make the n-tank,
      as shown in <cnxn target="fig1"/>. (You should go back and
      follow along with the cross-sectional views of the process, as
      we review looking at things from the top.)
      
      <figure id="fig1">
	<name>Implanted n-Tank</name>
	<media type="image/png" src="5.37.png"/>
      </figure>

      A mask opposite to that of the n-tank allows us to an n-channel

      <m:math>
	<m:msub>
	  <m:mi>V</m:mi>
	  <m:mi>T</m:mi>
	</m:msub>
      </m:math>

      adjust. We next deposit and pattern the nitride for the active
      regions, and grow the field oxide (FOX) <cnxn target="fig2"/>.

      <figure id="fig2">
	<name>Growing FOX</name>
	<media type="image/png" src="5.38.png"/>
      </figure>
      
      We remove the nitride, and deposit and pattern the poly., as seen
      in <cnxn target="fig3"/>

      <figure id="fig3">
	<name>Gate Poly Pattern</name>
	<media type="image/png" src="5.39.png"/>
      </figure>

      <cnxn target="fig4"/> shows what the two masks look like for the
      n+ and p+ source/drain implants:

      <figure id="fig4">
	<name>S/D Implants</name>
	<media type="image/png" src="5.40.png"/>
      </figure>

      Note that the gate poly extends beyond where the implant is
      being performed (inside the dotted line). This is a
      <emphasis>design rule</emphasis> which is the way the circuit
      designer takes into account the fact that the manufacturing
      process must have some tolerance built in, because things will
      not always be lined up just perfectly. Now we make some contact
      holes, seen in <cnxn target="fig5"/>:

      <figure id="fig5">
	<name>Etching Contact Holes</name>
	<media type="image/png" src="5.41.png"/>
      </figure>

      And finally, we sputter and pattern the metallization, which is
      depicted in <cnxn target="fig6"/>. You should go back to <cnxn document="m11350">MOSFETs</cnxn>, and convince yourself that the
      circuit shown in <cnxn target="fig1"/> is indeed what has been
      constructed in <cnxn target="fig6"/>. See if you can identify
      all of the correct parts. Note that there is a connection
      between

      <m:math>
	<m:msub>
	  <m:mi>V</m:mi>
	  <m:mi>ss</m:mi>
	</m:msub>
      </m:math>

      (ground) and the p-substrate <emphasis>very</emphasis> close to
      the n-channel source. There is also a contact between the n-moat
      and

      <m:math>
	<m:msub>
	  <m:mi>V</m:mi>
	  <m:mi>dd</m:mi>
	</m:msub>
      </m:math>

      which is <emphasis>very</emphasis> close to the p-channel
      source.  What advantage would this have? Hint: review the
      discussion of <cnxn document="m11361">latch-up</cnxn>.

      <figure id="fig6">
	<name>Metallization Patterning</name>
	<media type="image/png" src="5.42.png"/>
      </figure>  
    </para>
  </content>
  
</document>
