Frequency Shift Keying (FSK) is a scheme to transmit digital information across an analog channel. Binary data bits are grouped into blocks of a fixed size, and each block is represented by a unique carrier frequency, called a symbol, to be sent across the channel. 1 This requires having a unique symbol for each possible combination of data bits in a block. In this laboratory exercise each symbol represents a two-bit block; therefore, there will be four different symbols.

The carrier frequency is kept constant over some number of samples known as the symbol period ( T symb T symb ). The symbol rate, defined as F symb F symb , is a fraction of the board's sampling rate, F s F s . For our sampling rate of 44.1 kHz and a symbol period of 32, the symbol rate is 44.1k/32 symbols per second.

Figure 1: Pseudo-noise sequence generator and FSK transmitter.

The input bits to the transmitter are provided by the special shift-register, called a pseudo-noise sequence generator (PN generator), on the left side of Figure 1. A PN generator produces a sequence of bits that appears random. The PN sequence will repeat with period 2B−1 2 B 1 , where B B is the width in bits of the shift register. A more detailed diagram of the PN generator alone appears in Figure 2.

Figure 2: PN generator.

As shown in Figure 2, the PN generator is simply a shift-register and XOR gate. Bits 14 and 15 of the shift-register are XORed together and the result is shifted into the lowest bit of the register. This lowest bit is the output of the PN generator.

The PN generator is a useful source of random data bits for system testing. We can simulate the bit sequence that would be transmitted by a user as the random bits generated by the PN generator. Since communication systems tend to randomize the bits seen by the transmission scheme so that bandwidth can be efficiently utilized, the PN generator is a good data model.2

The shift-register produces one output bit at a time. Because each symbol the system transmits will encode two bits, we require the series-to-parallel conversion to group the output bits from the shift-register into blocks of two bits so that they can be mapped to a symbol.

This is responsible for mapping blocks of bits to one of four frequencies as shown in Figure 1. Each possible two-bit block of data from the series-to-parallel conversion is mapped to a different carrier frequency ω i ω i

One way to implement this mapping is by using a look-up table. The two-bit data block can be interpreted as an offset into a frequency table where we have stored the possible transmission frequencies. Note that since each frequency mapping defines a symbol, this mapping is done at the symbol rate F symb F symb , or once for every T symb T symb DSP samples.

The symbol bit assignments are such that any two adjacent frequencies map to data blocks that differ by only one bit. This assignment is called Gray coding and helps reduce the number of bit errors made in the event of a received symbol error.

In order to minimize the bandwidth used by the transmitted signal, you should ensure that the phase of your transmitted waveform is continuous between symbols; i.e., the beginning phase of any symbol must be equal to the ending phase of the previous symbol. For instance, if a symbol of frequency 9⁢π32 9 32 begins at phase 0, the symbol will end 31 output samples later at phase 31⁢9⁢π32 31 9 32 . To preserve phase continuity, the next output sample must be at phase 32⁢9⁢π32 32 9 32 , which is equivalent to phase π . Therefore, the next symbol, whatever its frequency, must begin at phase π . For each symbol, you must choose φ i φ i in the expression sin ω i ⁢n+ φ i ω i n φ i to create this continuity.