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Analog-to-Digital Converter on the MSP430

Module by: CJ Ganier

Summary: Explains how to use the MSP430 analog-to-digital converter (ADC).

The analog to digital converter (ADC) on the MSP430F169 is a 12 channel, 12 bit converter. The module is highly configurable and can run largely free of program involvement. In this portion of the lab, we will broadly explain the features of the module, but the particular effects of each register are listed, as usual, in the User’s Guide.

Range of Measurement

The result of each conversion will be 12 bits long in the form of an unsigned integer whose value is: 4095x (Vin – Vrneg)/ (Vrpos – Vrneg) Where Vin is the input voltage to be measured, Vrneg is the lower reference voltage, and Vrpos is the higher reference voltage. The reference voltages are set to power and ground by default (3.3V and 0V), but they can be changed to several other possibilities using the ADC12 Conversion Memory Control Registers (ADC12MCTLx). This allows each sample to choose its own voltage references. This register also allows for selection of the input channel for each sample. The highest bit of the register is used for multi-channel sequences. This EOS bit indicates the last sample of a sequence.

Operation Modes of the ADC

The ADC12 has four basic operation modes:

  1. Single channel, single conversion This mode corresponds to a request by the processor for a single sample from a single channel. Interrupts can still be used to indicate when the conversion is complete. The ADC will write the conversion to the ADC12MEMx cell indicated by the CSTARTADDx bits.
  2. Single channel, repeated conversions This mode uses a single ADC12MEMx cell as indicated by the the CSTARTADDx bits. Because this mode only uses a single memory cell, the results must be collected after each conversion. The interrupt flag is set after each conversion.
  3. Multiple channels, single conversion each A sequence is set up using the ADC12MCTLx registers to configure each memory slot to sample with the desired parameter. Each cell will take one sample before the sequence will need to be reinitiated. An interrupt flag will be set after each conversion.
  4. Multiple channels, repeated conversions A sequence is set up using the ADC12MCTLx registers to configure each memory slot to sample in the desired way. The sequence will repeat with the interrupt flag being set after each sample.
For each mode, a complete state machine diagram of the procedure is shown in the User’s Guide (chapter 17). The particular mode is chosen via the CONSEQx bits of the ADC12 Control Register 1 (ADC12CTL1). The conversions are generally started by setting the ADC12 Start Conversion bit (ADC12SC) or ADC12 Control Register 0 (ADC12CTL0).

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