Bus Interfaces

In both circuit board and chip level design, moving data from one part of the design to another is a major consideration. The traditional way to move information between devices or between elements of a single device is with some form of wire. For the wire traces on a PCB board, a group of traces or signals associated with the same data transmission is called a bus.

Buses generally fit into one of two categories: Parallel buses reserve a separate wire for each bit of a transmitted byte. Serial buses send the bits of a byte on the same wire, sequentially in time. There are cases of buses that blend these categories, but most bus protocols fall into one or the other. Serial buses are much slower but save a proportionally large amount of space.

Buses can also be categorized as synchronous or asynchronous. Synchronous buses send an additional clock signal to keep the communicating parties in sync with each other. This makes the communications protocols easier to implement in hardware. The chip controlling the clock signal determines the baud rate of the bus. The baud rate of a bus is the number of bits per second that can be transmitted on the bus including overhead. Asynchronous buses do not have a clock signal going between communicating parties so the baud rate is generally agreed to in advance and the correct phase is “inferred” from the transmission. Asynchronous buses save board space, but often have more communications overhead.

Other attributes of buses include what kind of parity, if any, it uses. Parity is the inclusion of an additional bit or bits with a byte to ensure correct transmission. Byte length, stop and start conventions, polarity, and bus voltage are all variable.

Below are described some examples of bus interfaces. There are many more. For complete descriptions of a bus interface, its best to read the data sheet for the parts that are going to use the bus because sometimes there are irregularities in the design that will deviate from the “standard” configuration. Timing diagrams, drawings, and charts are usually provided.

SPI Bus

SPI stands for serial port interface, and it is a four wire serial synchronous interface for communication between chips. The SPI protocol is also hierarchical, so one chip on the bus is the “master” who governs the clock and transmission schedule. The other three wires on the SPI are “master output slave input” (MOSI), “master input slave output” (MISO), and “chip select” (CS or STE). Data from the master to the slave is sent over the MOSI line. Data from the slave to the master is sent over the MISO line. The STE line is used to wake the slave device, and this line must always be enabled during communication.

I2C

I2C stands for inter-integrated circuit control, and it is a two wire serial synchronous interface for communications between a master and many slaves. I2C is more strictly hierarchical than SPI because there are no chip select wires to resolve conflicts. The master generally controls the clock wire of I2C, and the data wire is used by whichever party is transmitting. Because there can be many slaves on the bus, the first byte a master transmits in an I2C packet tells the slaves which one of them is the designated recipient of the message.