There are a few separate categories of instructions:

Arithmetic

add, sub, mul, div, inc, dec

Logical

xor, or, and, not

Floating-point

fadd, fsub, fmul, fdiv

Bit-wise

shl, shr, rol, ror

Stack

push, pop

Memory

get, put

Flow-control

cmp, jmp, je, jne, jl, jg

Subroutine

call, ret

System

int

Cache contributes greatly to the performance of a given processor. To enable high-performance applications to be implemented for this architecture, there will be at least 512K L1, 4M L2, and 8M L3 on-board cache for a 128-bit processor. For the 256-bit implementation, there should be at least 1M L1, 8M L2, and 16M L3 cache on-board. For very small operating systems, it is conceivable that the OS could always stay resident in the cache of one of the processors in a multi-processing system. If the applications being run were small enough, the OS could even stay resident in the cache of a single-CPU system.

One of the over-arching needs of any new processing architecture is to have lots of general-purpose registers (GPR). Registers, which sit on the processor, are substantially faster than hitting memory. To achieve this goal, my proposed architecture will have as many registers as the size of the architecture. If this instruction-set is implemented in a 128-bit processor, their will be 128 GPRs. (r0..r127). On the other hand, if this is implemented in a 256-bit CPU, there should be 256 GPRs (r0..r255).

There is also the need for a few special-purpose registers:

In addition to the normal GPRs, there will be a second ‘stack’ of registers to handle overflow in mathematical operations. Two 128-bit operands could yield a 256 result in a multiplication operation, so there will be a set of registers s0..s127 in a 128-bit CPU to handle the potential overflow in the result. Additionally, divisions will use the full double-architecture-width register (e.g. s2-r2) when performing a division. The second stack of registers will be the ‘high half’ of the result in multiplying, and the dividend in a division operation.

Every instruction will follow the same basic form, with all operations working on a register value. Only get and put will access memory. Binary operations - such as add, sub, and, etc - can either use two registers or a register and a constant.

There are myriad potential benefits of large processor architectures. The first is that, relatively speaking, infinite quantities of RAM and storage space can be directly addressed. 2128 2 128 words of memory, presuming each word is 128 bits long, is in the range of 4 * 1040 4 * 10 40 bytes of memory. A 256-bit CPU could theoretically address 2 * 1079 2 * 10 79 bytes of memory! Realistically, this much storage will never be available to us. And, if the memory addresses are actually encoded in a word-length instruction along with the register to use and the instruction itself, there would only be 6 * 1035 6 * 10 35 bytes addressable. This is still well beyond the capabilities of any machine to enclose, and should, therefore, provide for nearly infinite use of this architecture into the distant future.

Other benefits from using such a large architecture come in the scientific processing world. Computer scientists constantly need to think about the level of precision their machines can handle. Even top-end supercomputers cannot handle the floating-point operations I described above. Large-scale simulations, such as those performed by the ‘Earth Simulator’ in Japan, could have their accuracy greatly enhanced by using larger architectures. Floating-point round-off error in 256 or 512 bits is not worrisome to the vast majority of the scientific community.

Other possible uses for this processor include engineering workstations, data-mining servers, dedicated cryptography machines, and the high-end graphics market. A wide data path, such as the one described in this article, makes implementing and executing most encryption algorithms simple. Most encryption algorithms operate on large chunks at a time, such as the Advance Encryption Standard, which uses either 128- or 256-bit blocks in the rounds of its algorithm.

Performing advanced data analysis and mining using a machine that could directly address all of the storage in use on the planet would be a statistician’s dream. Engineers and graphics professionals alike would see their productivity enhanced by having more of their calculations performed more directly rather than in extremely segmented chunks as it is on current, common-off-the-shelf hardware.

Overall, I believe the processor manufacturing industry needs to take a quantum leap forward in technology. Recently, AMD and Intel have introduced 64-bit extensions to the ubiquitous x86 architecture. DEC gave us the Alpha CPU several years ago, and Apple uses IBM’s Power5 processor in its newest desktop machines. Shifting from 32- to 64-bit computing is a welcome change for those among us who are at the edge of exceeding the abilities of 32-bit processors and their inherent limitations, but why stop there? Why not take that extra step now to ensure that we won’t have to make another architectural change in another decade or two?

There is a similar shift taking place in moving from the current IPv4 to IPv6 addressing schemes for computer networks, going directly from 32-bit to 128-bit addresses. This change will take us from approximately 4 billion available nodes on the network to about one mole of addresses per square yard of the earth’s surface.

Let’s make this change sooner, rather than later.