<?xml version="1.0" encoding="utf-8"?>
<document xmlns="http://cnx.rice.edu/cnxml" xmlns:m="http://www.w3.org/1998/Math/MathML" xmlns:md="http://cnx.rice.edu/mdml/0.4" xmlns:bib="http://bibtexml.sf.net/" xmlns:q="http://cnx.rice.edu/qml/1.0" id="new" module-id="" cnxml-version="0.6">
  <title>An algorithm to implement a boolean function using only NAND's or only NOR's.</title>
  <metadata xmlns:md="http://cnx.rice.edu/mdml/0.4">
  <!-- WARNING! The 'metadata' section is read only. Do not edit below.
       Changes to the metadata section in the source will not be saved. -->
  <md:content-id>m13240</md:content-id>
  <md:title>An algorithm to implement a boolean function using only NAND's or only NOR's.</md:title>
  <md:version>1.4</md:version>
  <md:created>2006/01/04 14:23:33 US/Central</md:created>
  <md:revised>2009/07/01 13:45:35.119 GMT-5</md:revised>
  <md:authorlist>
    <md:author id="kef">
        <md:firstname>Katherine</md:firstname>
        <md:othername>E</md:othername>
        <md:surname>Fletcher</md:surname>
        <md:fullname>Katherine Fletcher</md:fullname>
        <md:email>kef@rice.edu</md:email>
    </md:author>
  </md:authorlist>
  <md:maintainerlist>
    <md:maintainer id="kef">
        <md:firstname>Katherine</md:firstname>
        <md:othername>E</md:othername>
        <md:surname>Fletcher</md:surname>
        <md:fullname>Katherine Fletcher</md:fullname>
        <md:email>kef@rice.edu</md:email>
    </md:maintainer>
  </md:maintainerlist>
  <md:license href="http://creativecommons.org/licenses/by/2.0/"/>
  <md:licensorlist>
    <md:licensor id="kef">
        <md:firstname>Katherine</md:firstname>
        <md:othername>E</md:othername>
        <md:surname>Fletcher</md:surname>
        <md:fullname>Katherine Fletcher</md:fullname>
        <md:email>kef@rice.edu</md:email>
    </md:licensor>
  </md:licensorlist>
  <md:keywordlist>
    <md:keyword>DeMorgan's Law</md:keyword>
    <md:keyword>Gate conversion</md:keyword>
    <md:keyword>Logical Completeness</md:keyword>
  </md:keywordlist>
  <md:subjectlist>
    <md:subject>Science and Technology</md:subject>
  </md:subjectlist>
  <md:abstract>An algorithm to implement a boolean function as a gate network using only NAND's or only NOR's is presented. Any boolean function can be implemented straightforwardly using AND's, OR's, and NOT gates. Using DeMorgan's Law in different forms gates in the network can be successively converted to use only NAND's or only NOR's.</md:abstract>
  <md:language>en</md:language>
  <!-- WARNING! The 'metadata' section is read only. Do not edit above.
       Changes to the metadata section in the source will not be saved. -->
</metadata>
  <content>
    <para id="element-980">NAND's and NOR's are the most common basic logic circuit element in use because they are simpler to build than AND and OR gates, and because each is <term target-id="complete"> logically complete </term>. Many logical functions are expressed using AND's, OR's, and Inverters (NOT), however, because an implementing circuit can be constructed straightforwardly from the truth table expression of a logical function and because <term target-id="karnaugh"> Karnaugh Map's </term> can be used to minimize AND, OR, INVERTER networks. </para>

<para id="element-1002"> This document is adapted, with permission, from algorithms and examples given in <cite target-id="jump326"><cite-title> Dr. Jump's Elec326 course notes. </cite-title></cite> </para>

<para id="element-981">Below a simple algorithm is given for converting a network with AND gates, OR gates and INVERTERS to one with  NAND gates or NOR gates exclusively. First the boolean function is represented using AND's, OR's, and NOT gates. Then, using DeMorgan's Law in various forms, the AND, OR, INVERTER network is converted step-by-step to use only NAND gates or only NOR gates.  
 
<table id="table14" summary="">
<title>DeMorgan's Law using Boolean Algebra</title>
<tgroup cols="2">
<colspec colname="c2" colnum="2"/>
<tbody>
<row> <entry> OR to NAND </entry>
       <entry> AND to NOR </entry> </row>
        <row>  <entry> <m:math><m:mrow><m:mrow><m:mrow><m:ci>a</m:ci><m:mo>∨</m:mo><m:ci>b</m:ci></m:mrow></m:mrow><m:mo>≡</m:mo><m:mo>¬</m:mo><m:mrow><m:mo>(</m:mo><m:mrow><m:mo>¬</m:mo><m:ci>a</m:ci></m:mrow><m:mo>∧</m:mo><m:mrow><m:mo>¬</m:mo><m:ci>b</m:ci></m:mrow><m:mo>)</m:mo></m:mrow></m:mrow></m:math>
          </entry>
          <entry> <m:math><m:mrow><m:mrow><m:mrow><m:ci>a</m:ci><m:mo>∧</m:mo><m:ci>b</m:ci></m:mrow></m:mrow><m:mo>≡</m:mo><m:mo>¬</m:mo><m:mrow><m:mo>(</m:mo><m:mrow><m:mo>¬</m:mo><m:ci>a</m:ci></m:mrow><m:mo>∨</m:mo><m:mrow><m:mo>¬</m:mo><m:ci>b</m:ci></m:mrow><m:mo>)</m:mo></m:mrow></m:mrow></m:math>
          </entry>
    </row>

</tbody>
</tgroup>
</table>


</para><figure id="element-7"><title>DeMorgan's Laws Illustrated Using Logic Gates</title>
<media id="id13239293" alt=""><image src="demorgans.jpg" mime-type="image/jpeg"/></media>
<caption>The figure is adapted with permission from <cite target-id="jump326"><cite-title> Dr. Robert Jump's Elec326 lecture notes </cite-title></cite>. The first two rows of the figure above illustrate DeMorgan's Law using gates. The third row illustrates how to eliminate any inverters with either NAND or NOR gates.</caption></figure><list id="element-911" list-type="enumerated"><title> Conversion Algorithm </title>
<item> Draw AND, OR, INVERTER implementation. First draw out an implementation of the boolean function using AND gates, OR gates and INVERTERS. Any implementation that uses only those three gate types will work. One way to implement a boolean function using AND's, OR's and INVERTERS is to build the <term> Disjunctive Normal Form </term> of the boolean function from the truth table that describes the function. Disjunctive Normal Form, is also called <term> Sum of Products </term> form.  <link document="m12075" class="cnxn"> Propositional Logic: Normal Forms  </link> gives a succinct treatment of normal forms and of how to go from a truth table to Disjunctive Normal Form.</item>


<item>Apply DeMorgan's Law. Apply DeMorgan's Law to the circuit by using the equivalences in the first two rows of the Figure above. To create a NAND only circuit, use the transforms in the left box, and for a NOR only circuit use the transforms in the right-hand box. </item>

<item>Remove redundant inverters: Any time that two inverters are in series (an inverted output goes directly in to an inverted input), remove both of them, since they cancel each other out.</item>

<item>Replace remaining inverters. Replace any remaining inverters with the equivalent NAND or NOR implementation (the third row of the Figure). </item></list><example id="element-692"><figure id="element-438"><title>Conversion Example</title>
<media id="id13239807" alt=""><image src="conversion.png" mime-type="image/png"/></media>
<caption>Example conversion to a NAND only network. </caption></figure><para id="element-553"> 

Note that in step c. the final elimination of inverters isn't quite done since B and D are inverted into one of the NAND's. 

</para>
</example> 

</content>

<glossary>
  <definition id="karnaugh">
    <term>Karnaugh Map</term>
    <meaning id="id13239865">A visual map of the truth table of a boolean expression and an algorithm for removing redundant elements to realize a minimized boolean expression.</meaning>
  </definition>
  <definition id="complete">
    <term>logically complete</term>
    <meaning id="id13239894">A set of circuit gates or logical elements is logically complete if any boolean function representable by a truth table can be realized using only gates or elements from that set.</meaning>
    <example id="def">
      <para id="par">
	AND, OR, and NOT is a logically complete set. NAND is logically complete. NOR is logically complete.
      </para>
    </example>
  </definition>
</glossary>

<bib:file>
  <bib:entry id="jump326">
    <bib:book>
      <bib:author>Robert Jump</bib:author>
      <bib:title>NAND/NOR Networks</bib:title>
      <bib:publisher>Unpublished course notes from Elec 326</bib:publisher>
      <bib:year>2004</bib:year>
      <bib:address>Rice University, Department of Electrical and Computer Engineering, Houston TX 77251</bib:address>
    </bib:book>
  </bib:entry>

</bib:file>
  
</document>
