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    "Basic setup for clocks on the MSP430."

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3.3 - Lab 3: Clocking on MSP430

Module by: Naren Anand Based on: Lab 4: Clocking on MSP430 by adrian valenzuela

Summary: In this lab, we will cover various timing options for the MSP430.

The following exercise will show you how to manipulate the clocking system on the ez430. You will need to refer to the ez430's Schematic and User's Guide to correctly configure the clock as specified.

Exercise 1

Clock Setup

In order to easily check the state of the clock, output MCLK/SMCLK (they are both defaulted to the same source) from a pin header (HINT: Output the SMCLK from P1.4 on pin 6). Use the oscilloscope to observe the frequency of the clock, and to see the impact of the changes you will make.

  1. Without modifying the clock registers any further, at what clock rate is the processor running at? How is the clock currently configured in order to produce this built-in clock signal? In other words, what is the clock's source and how is the source configured?
  2. Write code that sets the DCOCLK to operate at 8MHz. You should be able to do it in just two lines of code. We will use this clock setup for all future programs unless otherwise noted.
  3. Using your new (8MHz) timer settings and your SOS light system from Lab 1, modify the code so that each "dot" and "dash" delay is for approximately the same ammount of time. Basically, generate the same behavior as the original version but using the new clock settings. What were the original (much slower) settings for the clock? What was changed in order to keep the original blink rate?

Exercise 2

VLO Clock Setup

The following is code to set the MSP430 to operate off of the VLO clock. The only problem is that it doesn't work. Macro definitions and logic operations are incorrectly used (although the comments are correct). Without adding or removing any lines of code, properly source the MSP430 off the VLO clock. 

WDTCTL & ~WDTPW + WDTHOLD;              // Stop watchdog timer
BCSCTL1 |= LFXT1S_2;                    // LFXT1 = VLO
IFG1 = OFIFG;                           // Clear OSCFault flag
__bis_SR_register(SCG1 + SCG0);         // Stop DCO
Now using these timer settings, repeat number 3 from this lab's problem 1.

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