Based on: Multirate Filtering: Implementation on TI TMS320C54x by Douglas L. Jones, Swaroop Appadwedula, Matthew Berry, Mark Haun, Jake Janovetz, Michael Kramer, Dima Moussa, Daniel Sachs, Brian Wade, Robert Morrison
Summary: You will implement a multirate system that includes three fininte impulse response filters.
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Before implementing the entire system shown in Multirate Processing:
Introduction, we recommend you design a system that
consists of a cascade of filters FIR 1 and FIR 2 without the
sample-rate compressor or expander. After verifying that the
response of your two-filter system is correct, proceed to
implement the complete multirate system and verify its total
response. At first, use fixed compression and expansion
factors of
In order to perform the processing at the lower sample rate, implement a counter in your code. Your counter will determine when the compressed-rate processing is to occur, and it can also be used to determine when to insert zeros into FIR 3 to implement the sample-rate expander.
Some instructions that may be useful for implementing your
multirate structure are the add and bcc (branch conditional)
instructions. You may also find the b
(branch) instruction useful. The conditional fields that can be used with bcc can be found on page 1-7 of the 55x Mnemonic Instruction Set.
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