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Phase-Locked Loop (PLL) Overview

Module by: Christopher Schmitz. E-mail the author

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Summary: This module presents a very short, high-level introduction to Phase-Locked Loops.

A Phase-Locked Loop (PLL) is a commonly-used tool in many aspects of Communications to create a Maximum-Likelihood estimate of a "noisy" sinusoid. At its most basic level, the PLL consists of three devices: a Phase Detector (PD), a loop filter (F(s)), and a Voltage-Controlled Oscillator (VCO). In short (and overly simplifying), the PD estimates the phase difference between two signals, the loop filter acts to smooth the estimate and improve noise rejection, and finally the VCO responds to the smoothed phase estimate to modify the PLL's frequency to match that of the reference signal. It is a control loop with a plant (the VCO) and a controller (the loop filter).

Figure 1: PLL Block Diagram.
High-Level View of PLL
High-Level View of PLL (ECE463PLLblockdiagram2.png)

The PLL-design goal is then to choose an appropriate loop filter that results in the desired transient and steady-state properties of the closed-loop system. Proper selection of the loop filter (more aptly named "controller") requires suitable models for both the PD and the VCO plus some information about the desired transient response, the latter of which is primarily dependent upon the system in which the PLL is to be operated.

References

  1. Floyd M. Gardner. (2005). Phaselock Techniques: 3nd Ed. Wiley.
  2. John G. Proakis. (1995). Digital Communications: 3nd Ed. McGraw-Hill.

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