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Phase-Locked Loop (PLL) Overview

Module by: Christopher Schmitz. E-mail the author

Summary: This module presents a very short, high-level introduction to Phase-Locked Loops.

A Phase-Locked Loop (PLL) is a commonly-used tool in many aspects of Communications to create a Maximum-Likelihood estimate of a "noisy" sinusoid. At its most basic level, the PLL consists of three devices: a Phase Detector (PD), a loop filter (F(s)), and a Voltage-Controlled Oscillator (VCO). In short (and overly simplifying), the PD estimates the phase difference between two signals, the loop filter acts to smooth the estimate and improve noise rejection, and finally the VCO responds to the smoothed phase estimate to modify the PLL's frequency to match that of the reference signal. It is a control loop with a plant (the VCO) and a controller (the loop filter).

Figure 1: PLL Block Diagram.
High-Level View of PLL
High-Level View of PLL (ECE463PLLblockdiagram2.png)

The PLL-design goal is then to choose an appropriate loop filter that results in the desired transient and steady-state properties of the closed-loop system. Proper selection of the loop filter (more aptly named "controller") requires suitable models for both the PD and the VCO plus some information about the desired transient response, the latter of which is primarily dependent upon the system in which the PLL is to be operated.

Figure 2: Functional PLL Block Diagram.
Functional View of PLL
Functional View of PLL (ECE463PLLblockdiagram4.png)
  • The operation of the PLL can be split into two modes: "Locked" and "Un-Locked"
  • Initially, the loop starts in the un-locked mode. In this mode, the VCO is "FREE-RUNNING" at some frequency, fo fo. Since not even the frequency matches the reference, the phase mismatch between the VCO and reference is inconsequential.
  • When the reference signal is applied to the Phase Comparitor, an error voltage, Ve, is developed at the output of the phase comparitor.
  • The VCO has an input/output characteristic described by the figure below where the input (control) voltage can generally be biased to select the free-running VCO frequency.
Figure 3: Biasing of the VCO to set free-running frquency.
Biasing of the VCO to set Free-running Frequency
Biasing of the VCO to set Free-running Frequency (VCO_bias.png)
  • The error voltage is filtered (smoothed) and applied to the VCO. The smooothed version of the error voltage serves as the control voltage of the VCO. This control voltage, Vc, drives the VCO output frequency, fo, away from the free-running frequency and toward the reference frequency, fr.
  • When the VCO output frequency, fo, is equal to the reference frequency, fr, the loop is said to be "Locked."
  • It can be shown that the "Locked" condition is stable. That is to say, once the loop is locked, it will stay that way unless a significant disturbance knocks it out of lock. Thus, the loop will track changes in the reference frequency as long as the reference frequency stays within the "tuning range" of the VCO and as long as the reference frequency doesn't change "too quickly."
  • The loop, once it is locked, will also try to track the phase of the reference signal. The degree to which this is possible depends on the type of filter, F(s), used. It also depends on the "gain constants" of the Phase Comparitor and VCO, although both of these can be easily compensated by a filter with its own adjustable gain.


  1. Floyd M. Gardner. (2005). Phaselock Techniques: 3nd Ed. Wiley.
  2. John G. Proakis. (1995). Digital Communications: 3nd Ed. McGraw-Hill.

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