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Formation of Silicon and Gallium Arsenide Wafers

Module by: Andrew R. Barron

Summary: Integrated circuits (ICs) and discrete solid state devices are manufactured on semiconductor wafers. The following focuses on the general principles and methods with regard to wafer formation.

Introduction

Integrated circuits ( IC5IC5 size 12{"IC" rSub { size 8{5} } } {}) and discrete solid state devices are manufactured on semiconductor wafers. Silicon based devices are made on silicon wafers, while III-V (13-15) semiconductor devices are generally fabricated on GaAs wafers, however, for certain optoelectronic applications InP wafers are also used. The electrical and chemical properties of the wafer surface must be well controlled and therefore the preparation of starting wafers is a crucial portion of IC and device manufacturing. In order to obtain high fabrication yields and good device performance, it is very important that the starting wafers be of reproducibly high quality. For example, the front surface must be smooth and flat on both a macro- and microscale, because high-resolution patterns (lithography) are optically formed on the wafer. In principle, cutting a crystal into thin slices and polishing one side until all saw marks are removed and the surface appears smooth and glossy could produce a suitable wafer. However, due in part to the brittleness of Si and GaAs crystals, as well as the increasing requirements of wafer cleanliness and surface defect reduction with ever decreasing device geometries, a very complex series of processing steps are required to produce analytically clean, flat and damage-free wafer surfaces.

The following focuses on the general principles and methods with regard to wafer formation. Detailed formulas, recipes, and specific process parameters are not given as they vary considerably among different wafer producers. However, in general, techniques for fabrication of Si wafers have generally become standardized within the semiconductor industry. In contrast, GaAs wafer technology is less standardized, possibly due to either (a) the similarity to silicon practices or (b) the lower production volume of GaAs wafers. There are two general classes of processes in the methodology of making wafers: mechanical and chemical. As both Si and GaAs are brittle materials, the mechanical processes for their wafer fabrication are similar. However, the different chemistry of Si and GaAs require that the chemical processes be dealt with separately.

Wafer Formation Procedures

Each of the processing steps in the conversion of a semiconductor ingot (formed by Czochralski or Bridgeman growth) into a polished wafer ready for device fabrication, results in the removal of material from the original ingot; between 1/3 and 1/2 of the original ingot is sacrificed during processing. Methods for the removal of material from a crystal ingot are classified depending on the size of the particles being removed during the process. If the removed particles are much larger than atomic or molecular dimensions the process is described as being macro-scale. Conversely, if the material is removed atom-by-atom or molecule-by-molecule then the process is termed micro-scale. A further distinction between various types of processes is whether the removal occurs as a result of mechanical or chemical processes. The formation of a finished wafer from a semiconductor ingot normally requires six machining (mechanical) operations, two chemical operations, and at least one polishing (chemical-mechanical) operation. Additionally, multiple inspection and evaluation steps are included in the overall process. A summary of the individual steps, and their functions, involved in wafer production is shown in Table 1.

Table 1. Summary of the process steps involved in semiconductor wafer production
Process Type Function
cropping mechanical removal of conical shaped ends and impure portions
grinding mechanical obtain precise diameter
orientation flatting mechanical identification of crystal orientation and dopant type
etching chemical removal of surface damage
wafering mechanical formation of individual wafers by cutting
heat treatment thermal annihilation of undesirable electronic donors
edge Contouring mechanical provide radius on the edge of the wafer
lapping mechanical provides requisite flatness of the wafer
etching chemical removal of surface damage
polishing mechano-chemical provides a smooth (specular) surface
cleaning chemical removal of organics, heavy metals, and particulates

Crystal Shaping

Although an as-grown crystal ingot is of high purity (99.9999%) and crystallinity, it does not have the sufficiently precise shape required for ready wafer formation. Thus, prior to slicing an ingot into individual wafers, several steps are needed. These operations required to prepare the crystal for slicing are referred to as crystal shaping, and are shown in Figure 1.

Figure 1: Schematic representation of crystal shaping operations: (a) remove crown and taper, (b) grind to required diameter, (c) grind flat, and (d) slice sample for measurements. Shaded area represents material removed.
Figure 1 (graphics1.jpg)

Cropping

The as-grown ingots have conical shaped seed (top) and tang (bottom) ends that are removed using a circular diamond saw for ease of further manipulation of the ingot (Figure 1a). The cuttings are sufficiently pure that they are cleaned and the recycled in the crystal growth operation. Portions of the ingot that fail to meet specifications of resistivity are also removed. In the case of silicon ingots these sections may be sold as metallurgical-grade silicon (MGS). Conversely, portions of the crystal that meet desired resistivity specifications may be preferentially selected. A sample slice is also cut to enable oxygen and carbon content to be determined; usually this is accomplished by Fourier transform infrared spectroscopic measurements (FT-IR). Finally, cropping is used to cut crystals to a suitable length to fit the saw capacity.

Grinding

The primary purpose of crystal grinding is to obtain wafers of precise diameter because the automatic diameter control systems on crystal growth equipment are not capable of meeting the tight wafer diameter specifications. In addition, crystals are seldom grown perfectly round in cross section. Thus, ingots are usually grown with a 1-2 mm allowance and reduced to the proper diameter by grinding Figure 1b.

Crystal grinding is a straightforward process using an abrasive grinding wheel, however, it must be well controlled in order to avoid problems in subsequent operations. Exit chipping in wafering and lattice slip in thermal processing are problems often resulting from improper crystal grinding. Two methods are used for crystal grinding: (a) grinding on center and (b) centerless grinding.

Figure 2 shows a schematic of the general set-up for grinding a crystal ingot on center. The crystal is supported at each end in a lathe-like machine. The rotating cutting tool, employing a water-based coolant, makes multiple passes down the rotating ingot until the requisite diameter is obtained. The center grinder can also be used for grinding the identification flats as well as providing a uniform ingot diameter. However, grinding the crystal on centers requires that the operator locate the crystal axis in order to obtain the best yield.

Figure 2: Schematic representation of grinding on center.
Figure 2 (graphics2.jpg)

Centerless grinding eliminates the problems associated with locating the crystal center. The centerless method is superior for long crystals; however, a centerless grinder is much larger than a center grinder of the same diameter capacity. In centerless grinding the ingot is supported between two wheels, a grinding wheel and a drive wheel. A schematic of the centerless grinder is shown in Figure 3. The axis of the drive wheel is canted with respect to that of the crystal ingot and the grinding wheel pushing the crystal ingot past the stationary (but rotating) grinding wheel, see Figure 3b.

Figure 3: Schematic representation of centerless grinding viewed (a) along and (b) perpendicular to the crystal axis.
Figure 3 (graphics3.jpg)

Orientation/Identification Flats

Following grinding of the ingot to the desired diameter, one or two flats are ground along the length of the ingot. The identification flats (one or two) are ground lengthwise along the crystal according to the orientation and the dopant type. After grinding the crystal on centers the crystal is rotated to the proper orientation, then the wheel is positioned with its axis of rotation perpendicular to the crystal axis and moved along the crystal from end to end until the appropriate flat size is obtained. An optical or X-ray orientation fixture may be used in conjunction with the crystal mounting to facilitate the proper orientation of the crystal on the grinder.

The largest flat is called the primary flat (Figure 1c) and is parallel to one of the crystal planes, as determined by X-ray diffraction. The primary flat is used for automated positioning of the wafer during subsequent processing steps, e.g., lithographic patterning and dicing. Other smaller flats are called "secondary flats" and are used to identify the crystal orientation (<111> versus <100>) and the material (n-type versus p-type). Secondary flats provide a quick and easy manner by which unknown wafers can be sorted. The flats shown schematically in Figure 4 are located according to a Semiconductor Equipment and Materials Institute (SEMI®) standard and are ground to specific widths, depending upon crystals diameter. Notches are also used in place of the secondary flat; however, the relative orientations of the notch and primary flat with regard to crystal orientation and dopant are maintained.

Figure 4: SEMI locations for orientation/identification flats.
Figure 4 (graphics4.jpg)

Etching

The cropping and grinding processes are performed with relatively coarse abrasive and consequently a great deal of subsurface damage results. Pits, chips, and cracks all contribute to stress in the cut wafer and provide nuclei for crack propagation at the edges of the finished wafer. If regions of stress are removed then cracks will no longer propagate, reducing exit chipping and wafer breakage during subsequent fabrication steps.

The general method for removing surface damage is to etch the crystal in a hot solution. The most common etchants for Si are based on the HNO3-HF HNO3-HF size 12{"HNO" rSub { size 8{3} } "-HF "} {} system, in which etchant modifiers such as acetic acid also commonly used. In the case of GaAs HCl- HNO3HNO3 size 12{"HNO" rSub { size 8{3} } } {} is the appropriate system. These etchants selectively attack the crystal at the damaged regions. After etching, the crystal is transferred to the slicing preparation area.

Wafering

The purpose of wafering is to saw the crystal into thin slices with precise geometric dimensions. By far, the most common method of wafering semiconductor crystals is the use of an annular, or inner diameter (ID), diamond saw blade. A schematic diagram of ID slicing technology is shown in Figure 5.

Figure 5: Schematic diagrams of ID slicing process.
Figure 5 (graphics5.jpg)

The crystal, when it arrives at the sawing area, has been ground to diameter, flatted, and etched. In order to slice it, the crystal must be firmly mounted in such a way that it can be completely converted to wafers with minimum waste. The crystal is attached with wax or epoxy to a mounting block, which is usually cylindrical in shape and of the same diameter as the ingot. Also, a mounting beam (or strip) is attached along the length of the crystal at the breakout point of the saw blade. This reduces exit chipping (breakage that occurs as the blade exits the crystal at the end of a cut) and also provides support for the sawn wafer until it is retrieved. Graphite or phenolic resins are common materials for the mounting block and beams, although some success has been obtained in mounting ingots using hydraulic pressure. The saw blade is a thin sheet of stainless steel (325 μm), with diamond bonded to its inner edge. This blade is mounted on a drum that rotates at ca. 2000 rpm. Saw blades 58 cm (≈23 inches) in diameter with a 20 cm (8 inches) opening are common, however, as wafer sizes increase larger blades are employed: 30 cm (12 inches) wafers are now common for Si. The blade moves relative to the stationary crystal at a speed of 0.05 cm/s, and the cutting process is water-cooled. Thus, considering that wafers are sliced sequentially (one at a time), the overall process is very slow. A further problem is that the kerf loss (loss due to the width of the blade) results in approximately 1/3 of the material being lost as saw dust. Finally, the depth of the drum onto which the blade is attached limits the length of the ingot section that is accessible. In order to overcome this problem, another style of ID blade saw was developed in which the blade is mounted on an air bearing and is rotated by a belt drive. This allows the entire length of the crystal ingot to be sliced.

Both silicon and GaAs crystals are grown with either the crystallographic <100> or <111> direction parallel to the cylindrical axis of the crystal. Wafers may be cut either exactly perpendicular to the crystallographic axis or deliberately off-axis by several degrees. In order to obtain the proper wafer orientation, the crystal must be properly oriented on the saw. All production slicing machines have adjustments for orientation of the crystal; however, it is usually necessary to check the orientation of the first slice in order to assure that all subsequent slices will be properly oriented.

Obvious variables introduced during the wafering process include: cutting rate, wheel speed, and coolant flow rate. However, the condition of the machines, such as alignment and vibration, is the most important variable followed by the condition of the blade. A deviated blade rim may cause taper, bow, or warp. Table 2 summarizes the types of deformations that can occur during wafering, their physical appearance and their characteristics.

Table 2. Deformed wafers and their characteristics.
Type of bow and warp Surface appearance Lattice curvature Comments
graphics6.jpg flat flat ideal
graphics7.jpg curved flat  
graphics8.jpg curved curved  
graphics9.jpg flat curved  
graphics10.jpg curved flat slips

Heat Treatment

As-produced Czochralski grown crystals often have a level of oxygen impurity that may exceed the concentration of dopant in the semiconductor material (i.e., Si or GaAs). This oxygen impurity has a deleterious effect on the semiconductor properties, especially upon subsequent thermal processing, e.g., thermal oxide growth or epitaxial film growth by metal organic chemical vapor deposition (MOCVD). For example, when silicon crystals are heated to about 450 °° size 12{ {} rSup { size 8{°} } } {}C the oxygen undergoes a transformation that causes it to behave as an electron donor, much like an n-type dopant. These oxygen donors, or "thermal donors", mask the true resistivity of the semiconductor because they either add additional carrier electrons to a n-type crystal or compensate for the positive holes in a p-type crystal. Fortunately, these thermal donors can be "annihilated" by heat treating the materials briefly in the range of 500-800 °° size 12{ {} rSup { size 8{°} } } {}C and then cooling quickly through the 450 °° size 12{ {} rSup { size 8{°} } } {}C region before donors can reform. In principle thermal donor annihilation can be performed on wafers at any time during their fabrication; however, it is usually best to perform the heat treatment immediately after wafering since sub-standard wafers may be rejected before additional processing steps are undertaken and thus limiting additional cost. Donor annihilation is a bulk effect, and therefore the thermal treatment can be performed in air, since any surface oxide that may form will be removed in subsequent lapping and polishing steps.

Lapping or Grinding

The as-cut wafers vary sufficiently in thickness to require an additional operation, the slicing operation does not consistently produce the required flatness and parallelism required for many wafer specifications, see Table 2. Since conventional polishing does not correct variations in flatness or thickness, a mechanical two-sided lapping operation is performed. Lapping is capable of achieving very precise thickness uniformity, flatness and parallelism. Lapping also prepares the surface for polishing by removing the sub-surface sawing damage, replacing it with a more uniform and smaller lapping damage.

The process used for lapping semiconductor wafers evolved from the optical lens manufacturing industry using principles developed over several hundred years. However, as the lens has a curved surface and the wafers are flat, the equipment for lapping wafers is mechanically simpler than lens processing machines. The simplest double-side lapping machine consists of two very flat counter-rotating plates, carriers to hold and move the wafers between the plates, and a device to feed abrasive slurry steadily between the plates. The abrasive is typically a 9 μm Al2O3Al2O3 size 12{"Al" rSub { size 8{2} } O rSub { size 8{3} } } {} grit. Commercial abrasives are suspended in water or glycerin with proprietary additives to assist in suspension and dispersion of the particles, to improve the flow properties of the slurry, and to prevent corrosion of the lapping machine. Hydraulics or an air cylinder applies lapping pressure with low starting pressure for 2 to 5 minutes, which is then increased through most of the process. The completion of lapping may be determined by elapsed time or by an external thickness sensing device. The finished process gives a wafer with a surface uniform to within 2 μm. Approximately 20 μm per side is removed during the lapping process.

Although lapping would appear to be simple in concept, the successful implementation of a production lapping operation requires the development of a technique and experience to achieve acceptable quality with good yields. Small adjustments to the rotation rates of the plates and carriers will cause the plates to wear concave, convex or flat.

As lapping is a messy process, various efforts have been made to avoid it or to substitute an alternative process. The most likely approach at present is grinding, in which the wafer is held on a vacuum chuck and a series of progressively finer diamond wheels is moved over the wafer while it is rotated on a turn table. Grinding gives a clearer surface than lapping, however, only one side may be ground at a time and the resulting flatness is not as good as that obtained by lapping.

Edge Contouring

The rounding of the edge of the wafer to a specific contour is a fairly recent development in the technology of wafer preparation. It was known by the early seventies that a significant number of device yield problems could be traced to the physical condition of the wafer edge. An acute edge affects the strength of the wafer due to: stress concentration, and a lowering of its resistance to thermal stress, as well as being the source of particle chip, breakage, and lattice damage. In addition, the particles originating from the chipped edges can, if present on the wafer surface, add to the defect density (D 00 size 12{ {} rSub { size 8{ {} rSub { size 6{0} } } } } {}) of the IC process reducing fabrication yield. Further problems associated with a square edge include the build-up of photoresist at the wafer edge. The solution to these process problems is to provide a contoured edge with a defined radius (r).

Chemical etching of wafers results in a degree of edge rounding, but it is difficult to control. Thus, mechanical edge contouring has been developed and the result has been a dramatic improvement in yields in downstream wafer processing. Losses due to wafer breakage are also reduced. The edge contouring process is usually performed in cassette-fed high speed equipment, in which each wafer is rotated rapidly against a shaped cutting tool (Figure 6).

Figure 6: Schematic illustration of edge contouring.
Figure 6 (graphics11.jpg)

Etching

The mechanical processes described above to shape the wafer leave the surface and edges damaged and contaminated. The depth of the work damage depends on the specific process, however, 10 μm is typical. Such damage is readily removed by chemical etching. Etching is used at multiple points during the fabrication of a semiconductor device. The discussion below is limited to etches suitable for wafer fabrication, i.e., non-selective etching of the entire wafer surface.

Wet Chemical Etching

The wet chemical etching of any material can be considered to involve three steps: (a) transportation of the reactants to the surface, (b) reaction at the surface, and (c) movement of the reaction products into the etchant solution (Figure 7). Each of these may be the rate limiting step and thus control the etch rate and uniformity. This effect is summarized in Table 3.

Figure 7: Schematic representation of the three steps involved in wet chemical etching: (i) diffusion of the chemical etch reagents through the boundary layer, (ii) chemical reaction at the surface, and (iii) diffusion of the reaction products into the etch solution through the boundary layer.
Figure 7 (graphics12.jpg)
Table 3. Effects of rate limiting step in semiconductor etching.
Rate limiting step Etching rate Results Comments
Diffusion of reagent to the surface slow etching(anisotropic) enhanced surface roughness
Reaction at semiconductor surface fast polishing(isotropic) ideal
Diffusion of reaction products from the surface slow polishing(isotropic) reaction product remains on surface

An etchant that is limited by the rate of reaction at the surface will tend to enhance any surface features and promote surface roughness due to preferential etching at defects (anisotropic). In contrast, if the etch rate is limited by the diffusion of the etchant reagent through a stagnant (dead) boundary layer near the surface, then the etch will result in uniform polishing and the surface will become smooth (isotropic). If removal of the reaction products is rate limiting then the etch rate will be slow because the etch equilibrium will be shifted towards the reactants. In the case of an individual etchant reaction, the rate determining step may be changed by rapid stirring to aid removal of reaction products, or by increasing the temperature of the etch solution, see Figure 8. The exact etching conditions are chosen depending on the application. For example, dilute high temperature etches are often employed where the etch damage must be minimized, while cooled etches can be used where precise etch control is required.

Figure 8: Typical etch rate versus temperature plot for a mixture of HF (20%), (45%) and (35%).
Figure 8 (graphics13.jpg)

Traditionally mixtures of hydrofluoric acid (HF), nitric acid ( HNO3HNO3 size 12{"HNO" rSub { size 8{3} } } {}) and acetic acid ( MeCO2HMeCO2H size 12{"MeCO" rSub { size 8{2} } H} {}) have been used for silicon, but alkaline etches using potassium hydroxide (KOH) or sodium hydroxide (NaOH) solutions are increasingly common. Similarly, gallium arsenide etches may be either acidic or basic, however, in both cases the etches are oxidative due to the use of hydrogen peroxide. A wide range of chemical reagents are commercially available in "transistor grade" purity and these are employed to minimize contamination of the semiconductor. Deionized water is commonly used as a diluent for each of these reagents and the concentration of commonly used aqueous reagents is given in Table 4.

The equipment used for a typical etchant process includes an acid (or alkaline) resistant tank, which contains the etchant solution and one or more positions for rinsing the wafers with deionized water. The process is batch in nature involving tens of wafers and the best equipment provides a means of rotating the wafers during the etch step to maintain uniformity. In order to assure the removal of all surface damage, substantial over-etching is performed. Thus, the removal of 20 μm from each side of the wafer is typical. Etch times are usually several minutes per batch.

Table 4. Weight percent concentration of commonly used concentrated aqueous reagents
Reagent Weight % Reagent Weight %
HCl 37 HF 49
H 2 SO 4 H 2 SO 4 size 12{H rSub { size 8{2} } "SO" rSub { size 8{4} } } {} 98 H 3 PO 4 H 3 PO 4 size 12{H rSub { size 8{3} } "PO" rSub { size 8{4} } } {} 85
HNO 3 HNO 3 size 12{"HNO" rSub { size 8{3} } } {} 79 HClO 4 HClO 4 size 12{"HClO" rSub { size 8{4} } } {} 70
MeCO 2 H MeCO 2 H size 12{"MeCO" rSub { size 8{2} } H} {} 99 H 2 O 2 H 2 O 2 size 12{H rSub { size 8{2} } O rSub { size 8{2} } } {} 30
NH 4 OH NH 4 OH size 12{"NH" rSub { size 8{4} } "OH"} {} 29    

Etching Silicon

The most commonly used etchants for silicon are mixtures of hydrofluoric acid (HF) and nitric acid ( HNO3HNO3 size 12{"HNO" rSub { size 8{3} } } {}) in water or acetic acid ( MeCO2HMeCO2H size 12{"MeCO" rSub { size 8{2} } H} {}). The etching involves a reduction-oxidation (redox) reaction, followed by dissolution of the reaction products. In the HF- HNO3HNO3 size 12{"HNO" rSub { size 8{3} } } {} system the HNO3HNO3 size 12{"HNO" rSub { size 8{3} } } {} oxidizes the silicon and the HF removes the reaction products from the surface. The overall reaction is shown in Eq. 1.

Si + HNO3HNO3 size 12{"HNO" rSub { size 8{3} } } {} + 6 HF → H2SiF6H2SiF6 size 12{H rSub { size 8{2} } "SiF" rSub { size 8{6} } } {} + HNO2HNO2 size 12{"HNO" rSub { size 8{2} } } {} + H2OH2O size 12{H rSub { size 8{2} } O} {} (1)

The oxidation reaction involves the oxidation of Si 00 size 12{ {} rSup { size 8{0} } } {} to Si 4+4+ size 12{ {} rSup { size 8{"4+"} } } {}, and it is auto-catalytic in that the reaction product promotes the reaction itself. The initial step involves trace impurities of HNO2HNO2 size 12{"HNO" rSub { size 8{2} } } {} in the HNO3HNO3 size 12{"HNO" rSub { size 8{3} } } {} solution, which react to liberate nitrogen dioxide ( NO2NO2 size 12{"NO" rSub { size 8{2} } } {}), Eq. 2 and 3.

HNO2HNO2 size 12{"HNO" rSub { size 8{2} } } {} + HNO3HNO3 size 12{"HNO" rSub { size 8{3} } } {}N2O4N2O4 size 12{N rSub { size 8{2} } O rSub { size 8{4} } } {} + H2OH2O size 12{H rSub { size 8{2} } O} {} (2)

N2O4N2O4 size 12{N rSub { size 8{2} } O rSub { size 8{4} } } {} → 2 NO2NO2 size 12{"NO" rSub { size 8{2} } } {} (3)

The nitrogen dioxide oxidizes the silicon surface in the presence of water, resulting in the formation of Si(OH)2 Si(OH)2 size 12{"Si" \( "OH" \) rSub { size 8{"2 "} } } {}and the reformation of HNO2HNO2 size 12{"HNO" rSub { size 8{2} } } {} (Eq. 4). The latter re-enters the reaction process in Eq. 2. The Si(OH)2Si(OH)2 size 12{"Si" \( "OH" \) rSub { size 8{2} } size 8{ }} {}decomposes to give SiO2SiO2 size 12{"SiO" rSub { size 8{2} } } {}, Eq. 5. Since the reaction shown in Eq. 2 is rate limiting, an induction period is observed. However, this is overcome by the addition of NO2NO2 size 12{"NO" rSub { size 8{2} rSup { size 8{ - {}} } } } {} ions in the form of [ NH4NH4 size 12{"NH" rSub { size 8{4} } } {}][ NO2NO2 size 12{"NO" rSub { size 8{2} } } {}].

Si 00 size 12{ {} rSup { size 8{0} } } {} + 2 NO2NO2 size 12{"NO" rSub { size 8{2} } } {} + 2 H2OH2O size 12{H rSub { size 8{2} } O} {}Si(OH)2 Si(OH)2 size 12{"Si" \( "OH" \) rSub { size 8{"2 "} } } {}+ 2 HNO2HNO2 size 12{"HNO" rSub { size 8{2} } } {} (4)

Si(OH)2Si(OH)2 size 12{"Si" \( "OH" \) rSub { size 8{2} } size 8{ }} {}SiO2SiO2 size 12{"SiO" rSub { size 8{2} } } {} + H2H2 size 12{H rSub { size 8{2} } } {} (5)

The final step of the etch process is the dissolution of the SiO2SiO2 size 12{"SiO" rSub { size 8{2} } } {} by HF (Eq. 6). Stirring serves to remove the soluble products from the reaction surface. The role of the HF is to act as a complexing reagent, and thus the reaction shown in Eq. 6 is known as a complexing reaction. The formation of water as a reaction product requires that acetic acid be used as a diluent (solvent) to ensure better control.

SiO2SiO2 size 12{"SiO" rSub { size 8{2} } } {} + 6 HF → H2SiF6H2SiF6 size 12{H rSub { size 8{2} } "SiF" rSub { size 8{6} } } {} + 2 H2OH2O size 12{H rSub { size 8{2} } O} {}(6)

The etching reaction is highly dependent on the relative ratios of the etchant reagents. Thus, if an HF-rich solution is used, the reaction is limited by the oxidation step (Eq. 4) and the etching is anisotropic, since the oxidation reaction is sensitive to doping, crystal orientation, and defects. In contrast, the use of a HNO3HNO3 size 12{"HNO" rSub { size 8{3} } } {}-rich solution produces isotropic etching since the dissolution process is rate limiting (Table 3). The reaction of HNO3HNO3 size 12{"HNO" rSub { size 8{3} } } {}rich solutions has been found to be diffusion-controlled over the temperature range 20-50 °° size 12{ {} rSup { size 8{°} } } {}C (Figure 8), and is therefore commonly employed for removing work damage produced during wafer fabrication. The boundary layer thickness (Figure 7) and therefore the dimensional control over the wafer is controlled by the rotation rate of the wafers. A common etch formulation is a 4:1:3 mixture of HNO3HNO3 size 12{"HNO" rSub { size 8{3} } } {} (79%), HF (49%), and MeCO2HMeCO2H size 12{"MeCO" rSub { size 8{2} } H} {} (99%). There are some etchant formulations that are based on alternative (or additional) oxidizing agents, such as: Br2Br2 size 12{"Br" rSub { size 8{2} } } {}, I2I2 size 12{I rSub { size 8{2} } } {}, and KMnO4KMnO4 size 12{"KMnO" rSub { size 8{4} } } {}.

Alkaline etching (KOH/ H2OH2O size 12{H rSub { size 8{2} } O} {} or NaOH/ H2OH2O size 12{H rSub { size 8{2} } O} {}) is by nature anisotropic and the etch rate depends on the number of dangling bonds which in turn are dependent on the surface orientation. Since etching is reaction rate limited no rotation of the wafers is necessary and excellent uniformity over large wafers is obtained. Alkaline etchants are used with large wafers where dimensional uniformity is not maintained during lapping. A typical formulation uses KOH in a 45% weight solution in H2OH2O size 12{H size 8{2}O} {} at 90 °° size 12{ {} rSup { size 8{°} } } {}C.

Etching Gallium Arsenide

Although a wide range of etches have been investigated for GaAs, few are truly isotropic. This is because the surface activity of the (111) Ga and (111) As faces are very different. The As rich face is considerably more reactive than the Ga rich face, thus under identical conditions it will etch faster. As a result most etches give a polished surface on the As face, but the Ga face tends to appear cloudy or frosted due to the highlighting of surface features and crystallographic defects.

As with silicon the etch systems involve oxidation and complexation. However, in the case of GaAs the gallium is already fully oxidized (formally Ga3+), thus, it is the arsenic (formally the arsenide ion, As 3-3- size 12{ {} rSup { size 8{"3-"} } } {}) that is oxidized by a suitable oxidizing agent (e.g., H2O2H2O2 size 12{H rSub { size 8{2} } O rSub { size 8{2} } } {}) to the soluble oxide, As2O3As2O3 size 12{"As" rSub { size 8{2} } O rSub { size 8{3} } } {} (Eq. 7). The gallium ions form the oxide