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A DSP Based Class D Audio Amplifier

Module by: Jacob Fainguelernt. E-mail the author

Summary: Class D amplifiers have proven a higher power efficiency performance against linear classes such as Class A, B and AB. Power losses on Class D amplifiers are mainly due to non-ideality of the output transistors, operating as switches, controlled by Pulse Width Modulators. This example describes a method for utilizing both the Enhanced Pulse Width Modulator (ePWM) and the Analog-to-Digital Converter (ADC) of the TMS320F2808™ digital signal controller as D-Class Audio amplifier. The method involves analog full bridge D-class power amplifier and analog low-pass filtering the amplified PWM signal to remove high frequency components, leaving only the audio-frequency content.

Introduction

Class D amplifiers have proven a higher power efficiency performance against linear classes such as Class A, B and AB. Power losses on Class D amplifiers are mainly due to non-ideality of the output transistors, operating as switches, controlled by Pulse Width Modulators.

This example describes a method for utilizing both the Enhanced Pulse Width Modulator (ePWM) and the Analog-to-Digital Converter (ADC) of the TMS320F2808™ digital signal controller as D-Class Audio amplifier. The method involves analog full bridge D-class power amplifier and analog low-pass filtering the amplified PWM signal to remove high frequency components, leaving only the audio-frequency content.

Hardware and Software Requirements

This example was originally developed using the following hardware and software:

  • MatLab R2008a
  • Code Composer Studio (CCS) v3.3
  • eZDSP-F2808 board.

Related Files

Principle of Operation

The amplifier comprises three main blocks (shown in Figure 1):

Figure 1: The Class-D Audio Amplifier
Figure 1 (Slide1.JPG)

Input Circuit:

This block interfaces with the audio source, attenuates it DC component and limits the input voltage to the ADC to the range 0 - 3.3V. The circuit contains also a DC-DC converter, for the DSP input buffer.

Figure 2: Input Circuit Schematics
Figure 2 (graphics2.jpg)

Digital Signal Controller

The TMS320F2808, converts the analog signal to a pair of PWM signals that feed the output stage (Please refer to section ). It operates with 100 MHz. The ADC samples the input signal at a 97.656.25 Ksps rate. The ePWM, generates PWM signal with a period of 102.4 μs and duty cycle proportional to the input signal level. The ePWM coupled with a D-Class output stage and a second order passive RLC filter, provides a DAC equivalent.

Sampling the Analog Input

The analog signal is converted to PCM values as shown in . The conversion is performed as described in Table 1. The ADC operates in a sampling rate of 97.656 KHz (100 MHz/1024).

Figure 3: Analog to Digital (PCM) Conversion
Figure 3 (graphics3.jpg)

Table 1: Analog to Digital Conversion

Table 1
Input Voltage (Vin) Digital Value(ADCRESULT)
V in < 0V V in < 0V size 12{V rSub { size 8{ ital "in"} } <0V} {} 0
0 V in < 3V 0 V in < 3V size 12{0 <= V rSub { size 8{ ital "in"} } <3V} {} 4096Vin34096Vin3 size 12{"4096"* { {V rSub { size 8{ ital "in"} } } over {3} } } {},
V in 3V V in 3V size 12{V rSub { size 8{ ital "in"} } >= 3V} {} 4095

PCM → PWM

The PCM values are converted to PWM as shown in Figure 4. A period of 102.4 msecs (1024 clock cycles) was chosen. The relation PCM Value/Full Range is translated to the duty cycle of the PWM. A duty cycle of 512 (50 %) corresponds to 50% of the full range, for example. In this example sample values in the range 0-4095 will be mapped to duty cycle values (CMPA) in the range 0-1023, by dividing by 4 (shift right 2 bits), as shown in Figure 5.

Figure 4: PWM based Digital to Analog Conversion
Figure 4 (graphics4.jpg)

Figure 5: PCM to Duty Cycle Conversion
Figure 5 (graphics5.jpg)

The Interrupt Service Routine

The process described in the previous section is executed in the Interrupt Service Routine (ISR). The ADC conversion is triggered by the ePWM block when the PWM period starts (every 102.4 msecs). The ADC generates an interrupt at the end of conversion. The interrupt service routine updates the PWM duty cycle (CMPA value) on the value of this sample. The new duty cycle will be loaded in the beginning of the next PWM period. The process is described in Figure 6.

Figure 6: Timing Diagram
Figure 6 (graphics6.jpg)

Output Stage:

This module contains the H-bridge, and a Low Pass Filter to remove high frequency components, leaving only the audio-frequency content. This module basically implements a Digital to Analog Converter using a PWM signal generator and a Low Pass Filter as shown in . This method is described in .

Figure 7: PWM based Digital to Analog Conversion
Figure 7 (graphics7.jpg)

The basic configuration of a D-Class amplifier is the Half-Bridge (H-Bridge) configuration. Two output transistors operate as switches, driven by complementary PWM signals. One of the transistors is off (current through it is close zero), while the remaining one is on (voltage across it is close to zero), keeping the power dissipation very low.

Figure 8: H-Bridge Power Topology
Figure 8 (graphics8.jpg)

The full-bridge Class D amplifier comprises two half bridges, driven by synchronized PWM signals, having two alternate conduction paths through the load, each one having a pair of transistor conducting while the remaining pair is off.

Figure 9: Output Stage Schematics
Figure 9 (graphics9.jpg)

Implementation

This section will describe the process of building a Simulink model for code generation according to description in chapter .

In the first part the framework for interrupt handling will be created. The second section will describe the creation of the Interrupt Service Routine.

Interrupt

  1. Create a new Simulink model:
  2. Add the "F2808 eZDSP" block from the Target Support Package TC2.:
    Figure 10: The "F2808 eZDSP" block
    Figure 10 (graphics10.png)
  3. Add the "Hardware Interrupt" block from the C2808 DSP Chip Support group of the Target Support Package TC2. :
    Figure 11: The "Hardware Interrupt" Block
    Figure 11 (graphics11.png)
    The Interrupt should be generated at the end of conversion of group A, (CPU Values=1 and PIE Values=1) as shown in Figure 12.
    Figure 12: The "Hardware Interrupt" Selection Table
    Figure 12 (Interrupt Table.jpg)
  4. Double-click the Hardware Interrupt block and configure it as follows::
    Figure 13: The Hardware Interrupt Configuration
    Figure 13 (graphics13.png)
  5. Add the "Function-Call Subsystem" block from the Ports and Subsystems group of the Simulink blockset.:
    Figure 14: The "Function-Call Subsystem" Block
    Figure 14 (graphics14.png)
  6. Connect the blocks as shown in Figure 15. Save the model as "eZDSPF2808ClassD".: 1
    Figure 15: The Class-D Amplifier Model
    Figure 15 (graphics15.png)

PCM to PWM Conversion

  1. Double-click the Function-Call Subsystem block and delete the "In1" and Out1 blocks.:
    Figure 16
    Figure 16 (graphics16.png)
  2. Add the "ADC" block from the C2808 DSP Chip Support group of the Target Support Package TC2.:
    Figure 17: The "ADC" Block
    Figure 17 (graphics17.png)
    The block should be configured to use channel 0 of module A, triggered by ePWMxA, and post an interrupt at the end of conversion as shown:
    Figure 18: The "ADC" Configuration
    (a) (b)
    Figure 18(a) (fig17_1.JPG)Figure 18(b) (fig17_2.JPG)
  3. Add two copies of the "ePWM" block from the C2808 DSP Chip Support group of the Target Support Package TC2. Name them ePWM1 and ePWM2.:
    Figure 19: The "ePWM" block
    Figure 19 (graphics19.png)
    The blocks should be configured as shown in the following figures:
    Figure 20: The "ePWM1" block Configuration
    (a)
    Figure 20(a) (Slide_10.JPG)
    (b)
    Figure 20(b) (Slide11.JPG)
    (c)
    Figure 20(c) (Slide12.JPG)
    Figure 21: The "ePWM2" block Configuration
    (a)
    Figure 21(a) (Slide13.JPG)
    (b)
    Figure 21(b) (Slide14.JPG)
    (c)
    Figure 21(c) (Slide15.JPG)
  4. Add the "Shift Arithmetic" block from the Logic and Bit Operations group of the Simulink blockset, and configure it for shift 2 bits right. :
    Figure 22: The "Shift Arithmetic" Block
    Figure 22 (graphics22.png)
    Figure 23: The "Shift Arithmetic" Block Configuration
    Figure 23 (graphics23.png)
  5. Connect the blocks as shown in Figure 22.:
    Figure 24: The Class D Amplifier Model
    Figure 24 (fig.JPG)

Running the model:

  1. Connect the system as shown in the following figures::
    Figure 25: The System
    Figure 25 (Slide16.JPG)
    Figure 26: Voltage Supply
    Figure 26 (Slide17.JPG)
  2. Build and run the model "CTRL-B".
  3. The amplifier should start working, connect your audio source, and enjoy the music.

Things to Try

This example's objective was to show the use of the F2808 blocks, it is certainly not the best implementation, but it serves as the basis for additional features and enhancements like:

  • Use Oversampling
  • Use the High-Resolution PWM
  • Add Signal Processing (Filtering, Equalization, Gain Control) features to the amplifier

References

  1. "eZdspTM F2808 Technical Reference", Spectrum Digital, 2005 http://c2000.spectrumdigital.com/ezf2808/docs/2808_ezdspusb_techref_c.pdf
  2. David M. Alter, " Using PWM Output as a Digital-to-Analog Converter on a TMS320F280x", TI Application Report SPRAA88 , September 2008 http://www.ti.com/litv/pdf/spraa88a

Footnotes

  1. You may also change colors, and name the blocks as shown here.

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