Introduction
This laboratory gives examples of the uses of the ADC types available in the hardware development kits. A different laboratory is developed for each kit, taking into account that both the ADC10 and the SD16_A laboratories implement a temperature data logger. The ADC12 laboratory also uses operational amplifiers to perform the analogue signal conditioning.
Overview
This laboratory (Lab2_ADC.c) examines the ADC12 and OA modules using the MSP-EXP430FG4618 Development Tool (MSP430FG4618 device). The test voltage is generated by the DAC12 channel 0, available in DAC12_ODAT register. The analogue signal is conditioned by the OA module (amplitude change), configured as non-inverting operational amplifier. Afterwards, this signal is applied to the ADC12 input to be converted. Compare the DAC12_ODAT and the ADC12MEM0 values.
Resources
The DAC12 module uses the same internal reference voltage as the ADC12 module (VREF+ = 2.5 V).
The OA module is configured as Non-inverting PGA with unity gain. The Non-inverting input is the DAC0 internal while the output is connected to internal/external A1 of the ADC12. The ADC12 sample-and-hold time is configured to be 64 ADC12CLK cycles. It performs a single-channel, single-conversion using ADC12OSC/1 as the clock source.
The resources used by the application (following the signal modification steps) are:
- DAC12;
- OA;
- ADC12;
- Timer_A;
- Interrupts.
Software application organization
The laboratory is organized following its working flow chart:
- Peripheral initialization phase, finishing with the MSP430 in LPM3;
- ISR phase, consisting of a Timer_A overflow service routine that triggers a new ADC12 conversion and it is responsible by the end of conversion.
The application starts by stopping the Watchdog Timer.
The system clock is configured by the FLL+ at 4.199304 MHz (128 x 32768Hz).
The DAC12 module is configured to present a null voltage (0 V) at the output. It uses the ADC12 internal 2.5 V reference voltage. The DAC12’s output is configured with 12-bit resolution, in straight binary. DAC12 uses the full-scale output with a Medium speed/current.
The OA module is configured as non-inverting PGA, the input signal (DAC0 internal) being in the rail-to-rail range. The output of the OA is connected to internal/external A1.
The ADC12 is configured to perform a single-channel (channel A1), single-conversion. The configuration includes the activation of the same internal reference voltage as the DAC12. The ADC12 clock source is ADC12OSC, with the sample-and-hold time selected as 64 ADC12CLK cycles.
The Timer_A is configured to use the ACLK as the clock source. It will count in continuous mode (TACCR0 counts up to 0FFFFh) and generate an interrupt to update the ADC12MEM. When the interrupt is serviced, the MSP430 enters into LPM3.
System configuration
ADC12 configuration:
The ADC12 module is configured in order to have the following characteristics:
- Single-channel, single-conversion operation;
- Uses the internal signal VREF+ (2.5 V) as reference voltage;
- The sample-and-hold time must be 64 ADC12CLK cycles;
- The conversion result must be available on ADC12MEM0;
- The sample-and-hold clock source is defined by software.
ADC12CTL0 |= SHT02|REF2_5V|REFON|ADC12ON|ENC|ADC12SC;
//SHT1x (Sample-and-hold time) = 0000b -> N/A
//SHT0x (Sample-and-hold time) = 0010b -> 64 ADC12CLK
//MSC (Multiple sample and conversion) = 0b -> N/A
//REF2_5V (Reference generator voltage) = 1b -> 2.5 V
//REFON (Reference generator on) = 1b -> Reference on
//ADC12ON (ADC12 on) = 1b -> ADC12 on
//ADC12OVIE (overflow-int. enable) = 0b -> disabled
//ADC12TOVIE (conversion-time-overflow int enable) = 0b
// -> disabled
//ENC (Enable conversion) = 0b -> enable configuration
//ADC12SC (Start conversion) = 1b -> Start conversion
ADC12CTL1 = CSTARTADD_0; // Start MEM0, TB1, Rpt Sing.
//CSTARTADDx (Conv. start address.) = 0000b -> ADC12MEM0
//SHSx (Sample-and-hold source) = 00b -> ADC12SC bit
//SHP (Sample-and-hold pulse-mode select) = 0b
// -> SAMPCON is sourced from the sample-input signal
//ISSH (Invert signal S-H) = 0b -> not inverted
//ADC12DIVx (ADC12 clock divider) = 000b -> /1
//ADC12SSELx (ADC12 clock source) = 00b -> ADC12OSC
//CONSEQx (Conversion sequence mode) = 00b -> Single-
// channel, single-conversion
//ADC12BUSY (ADC12 busy) = xb -> read only
The ADC12 module operates with reference voltages: VR+ = VREF+ and VR- = AVSS. The channel selected to perform the analogue-to-digital conversion is channel A1. This channel is internally connected the OA0’s output.
ADC12MCTL0 = INCH_1 | SREF_1;
//EOS (End of sequence) = 0b -> Not Used
//SREFx (Select ref.) = 001b -> VR+=VREF+/VR-=AVSS
//INCHx (Input channel select) = 0001b -> A1
DAC12 configuration:
DAC12_0DAT = 0x00; // DAC_0 output 0V
DAC12_0CTL = DAC12IR | DAC12AMP_5 | DAC12ENC;
//DAC_0 -> P6.6
//DAC_1 -> P6.7
//DAC reference Vref
//12 bits resolution
//Immediate load
//DAC full scale output
//Medium speed/
//Straight binary
//Not grouped
OA0 configuration
The OA module of the MSP430FG4168 has three operational amplifiers with wide utilization flexibility. For this laboratory it is set up using the OA0 in non-Inverting PGA mode with the following configuration:
- The inverting input is connected to the DAC12 channel 0;
- The amplifier gain is configured as unity;
- The input is configured in rail-to-rail mode;
- The output is connected to the channel A1.
OA0CTL1 |= OAFC_4 | OAFBR_0;
//OAFBRx (feedback resistor) = 000b -> Tap 0 (G=1)
//OAFCx (OAx function) = 100b -> Non-inverting PGA
//OARRIP = 0b -> OAx input range is rail-to-rail
OA0CTL0 |= OAP_2 | OAPM_3 | OAADC1;
//OANx (Inverting input) = XXb -> not important
//OAPx (Non-inverting input) = 10b -> DAC0 internal
//OAPMx (Slew rate select) = 11b -> Fast
//OAADC1 (OA output) = 1b -> output connected to A1
//OAADC0 (OA output) = 0b -> output not connected A12
ADC12 ISR
#pragma vector=ADC12_VECTOR
__interrupt void ADC_ISR(void)
{
int x;
x = ADC12MEM0; // Reads data
ADC12CTL0 |= ADC12SC; // Start new conversion
}
Timer_A ISR
#pragma vector=TIMERA1_VECTOR
__interrupt void TimerA_ISR (void)
{
ADC12CTL0 &= ~ADC12SC; //start new conversion
TACTL &= ~TAIFG;
}
Analysis of operation
This laboratory uses the previous modules to construct an analogue signal chain as shown in Figure 1.
| Analogue signal chain structure. |
|---|
 |
The input voltage VIN is in the range 0 V and 2.5 V, with a resolution of:
ΔVIN = ( 2.5 x VREF ) / 212 = 0.6 mV
The VIN value is controlled by the value in the DAC12_0DATA register.
The output voltage Vo has the same characteristics as the input voltage, but scaled by a multiplication factor (gain), attributed by the OA. The OA gain is selectable through the OAFBR field in the OA0CTL1 register.
The Vo conversion result is stored in the ADC12MEM0 register.
Once the signal chain modules are configured in accordance with the previous steps, initiate the experiment by completing the file, compiling it and running it on the Experimenter’s board. For the evaluation of the peripherals discussed during this laboratory, set a breakpoint on the ADC12_ISR and perform the following operations:
- Configure the DAC12_0DATA register with the value 0xFF. With the aid of a voltmeter, measure the analogue input voltage A6 (DAC12 channel 0 output). The value should be in the region of 0.15 V;
- Measure the input voltage A1 (OA0’s output). The voltage value should be the same;
- Execute the code. Verify the ADC12’s conversion result. The value should be similar to the one of the DAC12_0DATA register;
- Double the amplifier gain (2x). Verify the voltage at A0. It should be the double of the input voltage A1 (OA0’s output) given in step 2;
- Execute the code. Verify the ADC12’s conversion result. The value should be two times the value of the DAC12_0DATA register;
- Execute further modifications in order to evaluate the digital-to-analogue and analogue-to-digital conversion. Do not exceed the Vo maximum value (2.5 V).
This example and many others are available on the MSP430 Teaching ROM.
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