Introduction
The MSP430 contains built-in features for both parallel and serial data communication. This chapter describes the operation of these peripherals, and discusses the protocols, data formats and specific techniques for each type of data communication.
The communication modules available for the MSP430 family of microcontrollers are USART (Universal Synchronous/Asynchronous Receiver/Transmitter), USCI (Universal Serial Communication Interface) and USI (Universal Serial Interface). These provide asynchronous data transmission between the MSP430 and other peripheral devices when configured in UART mode. They also support data transmission synchronized to a clock signal through a serial I/O port in Serial Peripheral Interface (SPI) and Inter Integrated Circuit (I2C) modes.
Overview
This laboratory explores the USCI and USI communication interfaces in I2C mode. It uses the two MSP430 devices included on the Experimenter’s board: MSP430FG4618 as the master and the MSP430F2013 as the slave. The master receives a single byte from the slave as soon as a button connected to P1.0 is pressed.
Resources
This laboratory uses the USCI module of the MSP430FG4618 device and the USI module included in the MSP430F2013. Both units operate in I2C mode.
The interrupts on the slave unit are generated exclusively by the USI module. They are:
- START condition in the I2C bus;
- Data reception and transmission.
The interrupts on the master unit are provided by the USCI module. They are:
- Data reception;
- Interrupt on Port1.
The resources used are:
- USCI module;
- USI module;
- Interrupts;
- I/O ports.
Software application organization
The software architecture for this laboratory is shown in Figure 1.
The master task is composed of two interrupt service routines ( Lab3_Comm_1.c):
- S1 switch service routine used to receive a new frame from the slave;
- USCI module interrupt service routine that reads the data sent by the slave.
Software architecture
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For the operational capability of the slave unit based on the USI module, it is necessary to implement a state machine as shown in Figure 2. It is important to note that the states “RX Address” and “RX (N)ACK" are transient states that ensure the USI module is prepared for the next activity.
Slave state machine.
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System configuration
USCI_B (master) control registers configuration
The connection via I2C bus will operate in the following mode:
- Address slave with 7-bit address;
- Master mode;
- Single master;
- USCI clock source is SMCLK;
The following control registers are configured based on these characteristics:
UCB0CTL0 = 0x0F;
//UCB0CTL0 = UCA10 | UCSLA10 | UCMM | Unused | UCMST | UCMODEx | UCSYNC
//UCA10 (Own address) = 0b -> Own address (7-bit)
//UCSLA10 (Slave address) = 0b -> 7-bit slave address
//UCMM (Multi-master) = 0b -> Single master
//Unused
//UCMST (Master mode) = 1b -> Master mode
//UCMODEx (USCI mode) = 11b -> I2C Mode
//UCSYNC (Synchronous mode enable) = 1b -> Synchronous
UCB0CTL1 = 0x81;
//UCB0CTL1 = UCSSELx | Unused | UCTR | UCTXNACK | UCTXSTP | UCTXSTT | UCSWRST
//UCSSELx (USCI clock source select) = 10b -> SMCLK
//Unused
//UCTR (Transmitter/Receiver) = 0b -> Receiver
//UCTXNACK (Transmit a NACK) = 0b -> ACK normally
//UCTXSTP (Transmit STOP condition) = 0b -> No STOP
//UCTXSTT (Transmit START condition) = 0b -> No START
//UCSWRST (Software reset) = 1b -> Enabled
Data rate USCI_B (master)
The system clock is configured to operate with a frequency of ~ 1048 kHz from the DCO. This frequency will be the working base frequency of the USCI module. The connection operates at a clock frequency of ~ 95.3 kHz:
// DATA RATE
// data rate -> fSCL = SMCLK/11 = 95.3kHz
UCB0BR0 = 0x0B; // fSCL = SMCLK/11 = 95.3kHz
UCB0BR1 = 0x00;
Port configuration USCI_B (master)
In order to set the external interfaces at the USCI module, it is necessary to configure the I/O ports. Select the USCI peripheral in I2C mode matching the connections provided at the Experimenter’s board:
P3SEL |=0x06; // Assign I2C pins to USCI_B0
USI (slave) control registers configuration
The connection via I2C bus will operate in the following mode:
- Slave mode;
- USI counter interrupt enable (RX and TX);
- START condition interrupt-enable;
- USIIFG is not cleared automatically.
The following control registers are configured based on these characteristics:
USICTL0 = 0XC1;
//USICTL0 = USIPE7 | USIPE6 | USIPE5 | USILSB | USIMST | USIGE | USIOE | USISWRST
//USIPE7 (USI SDI/SDA port enable) = 1b -> USI enabled
//USIPE6 (USI SDO/SCL port enable) = 1b -> USI enabled
//USIPE5 (USI SCLK port enable) = 0b -> SCLK disable
//USILSB (LSB first) = 0b -> MSB first
//USIMST (Master) = 0b -> Slave mode
//USIGE (Output latch control) = 0b -> Output latch
// enable depends on shift clock
//USIOE (Serial data output enable) = 0b -> Output enable
//USISWRST (USI software reset) = 1b -> Software reset
USICTL1 = 0x70;
//USICTL1 = USICKPH | USII2C | USISTTIE | USIIE | USIAL | USISTP | USISTTIFG | USIIFG
//USICKPH (Clock phase select) = 0b -> Data is changed
// on the first SCLK edge and captured on the following edge.
//USII2C (I2C mode enable) = 1b -> I2C mode enabled
//USISTTIE = 1b -> Interrupt on START condition enabled
//USIIE = 1b -> USI counter interrupt enable
//USIAL (Arbitration lost) = 0b -> Not used
//USISTP (STOP condition received) = 0b -> Not used
//USISTTIFG (START condition int. flag) = 0b -> Not used
//USIIFG (USI counter int. flag) = 0b -> No int. pending
The slave unit interrupt service routine is not complete. The portion related to the “I2C_TX” state needs to be completed:
- Configure the USI module as output;
- Insert the information to transmit using the transmission register;
- Configure the bit counter.
// USI Bit Counter Register
USICNT |= 0x20;
//USICNT = USISCLREL | USI16B | USIIFGCC | USICNTx
//USISCLREL (SCL release) = 0b -> SCL line is held low
// if USIIFG is set
//USI16B (16-bit shift register enable) = 0b -> 8-bit
// shift register mode
//USIIFGCC (USI int. flag clear control) = 1b -> USIIFG
// is not cleared automatically
//USICNTx (USI bit count) = 00000b -> (not relevant)
// I2C state machine:
USICTL0 |= USIOE; // SDA = output
USISRL = SlaveData; // Send data byte
USICNT |= 0x08; // Bit counter = 8, TX data
Analysis of operation
Once the USCI module is configured in accordance with the previous steps, initiate the experiment with the files ( Lab3_Comm_1.c) (master – MSP430FG4618) and ( Lab3_Comm_2.c) (slave – MSP430F2013), compiling them and running them on the Experimenter’s board.
For this laboratory, the following jumper settings are required:
- PWR1/2, BATT, LCL1/2, JP2;
- SPI: H1- 1&2, 3&4.
The slave data is sent and increments from 0x00 with each transmitted byte, which is verified by the Master. The LED is off for address or data Acknowledge and the LED turns on for address or data Not Acknowledge. LED3 blinks at each data request. It is turned on with a START condition and it is turned off by the data transmit acknowledge by the slave (Note: the I2C bus is not released by the master since the successive START conditions are interpreted as “repeated START”).
Verify the value received setting a breakpoint in the line of code “RxBuffer = UCB0RXBUF;” of the USCI interrupt.
This example and many others are available on the MSP430 Teaching ROM.
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