2.1 Memory Organization from the memory chip
Each memory chip contains a number of 1-bit cells. The 1, 4, and 16 million cell chips are common. The cells can be arranged as a single bit column (e.g., 4Mx1) or in multiple bits per address location (e.g., 1Mx4)
- To reduce pin count, address lines can be multiplexed with data and/or as high and low halves Trade off is in slower operation
- Typical control lines:
W* (write), OE* (output enable) for write and read operations
CS* (chip select) derived from external address decoding logic
RAS*, CAS* (row and column address selects) used when address is applied to the chip in 2 halves
- Example:
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Figure 11.1 Organization 256Kx8 memory from 256Kx1 chips
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Figure 11.2 . Mbyte Memory Organization
2.2 Error correction
- Problem: Semiconductor memories are subject to errors
– Hard (permanent) errors
» Environmental abuse
» Manufacturing defects
» Wear
– Soft (transient) errors
» Power supply problems
» Alpha particles: Problematic as feature sizes shrink
– Memory systems include logic to detect and/or correct errors
» Width of memory word is increased
» Additional bits are parity bits
» Number of parity bits required depends on the level of detection and correction needed
- General error detection and correction
– A single error is a bit flip -- multiple bit flips can occur in a word
– 2M valid data words
– 2M+K codeword combinations in the memory
– Distribute the 2M valid data words among the 2 M+K codeword combinations such that the “distance” between valid words is sufficient to distinguish the error
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Figure 11.3
- Single error detection and correction
– For each valid codeword, there will be 2K-1 invalid codewords
– 2K-1 must be large enough to identify which of the M+K bit positions is in error
– Therefore 2K-1 > M+K
» 8-bit data, 4 check bits
» 32-bit data, 6 check bits
– Arrange bits as shown in Figure 11.4
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Figure 11.4
– Bit position n is checked by bits Ci such that the sum of the subscripts, i, equals n (e.g., position 10, bit M6, is checked by bits C2 and C8)
To detect errors, compare the check bits read from memory to those computed during the read operation (use XOR)
+ If the result of the XOR is 0000, no error
+ If non-zero, the numerical value of the result indicates the bit position in error
+ If the XOR result was 0110, bit position 6 (M3) is in error
Double error detection can be added by adding another check bit that implements a parity check for the whole word of M+K bits. SED and SEC-DED are generally enough protection in typical systems
