Skip to content Skip to navigation

Connexions

You are here: Home » Content » DIGITAL CIRCUITS

Navigation

Lenses

What is a lens?

Definition of a lens

Lenses

A lens is a custom view of the content in the repository. You can think of it as a fancy kind of list that will let you see content through the eyes of organizations and people you trust.

What is in a lens?

Lens makers point to materials (modules and collections), creating a guide that includes their own comments and descriptive tags about the content.

Who can create a lens?

Any individual member, a community, or a respected organization.

What are tags? tag icon

Tags are descriptors added by lens makers to help label content, attaching a vocabulary that is meaningful in the context of the lens.

This content is ...

Affiliated with (What does "Affiliated with" mean?)

This content is either by members of the organizations listed or about topics related to the organizations listed. Click each link to see a list of all content affiliated with the organization.
  • VOCW

    This module is included inLens: Vietnam OpenCourseWare's Lens
    By: Vietnam OpenCourseWare

    Click the "VOCW" link to see all content affiliated with them.

Recently Viewed

This feature requires Javascript to be enabled.
 

DIGITAL CIRCUITS

Module by: Dinh Sy Hien. E-mail the author

Summary: This module presents the basic concepts of MOSFET digital logic circuits. We will examine NMOS logic circuits, which contain only n-channel transistors, and complementary MOS, or CMOS, logic circuits, which contain both n-channel and p-channel transistors. The NMOS inverter is the basic of NMOS digital logic circuits. We will analyze the dc voltage transfer characteristics of several inverter designs. We will also define and develop the noise margin of NMOS digital circuits in terms of the inverter voltage transfer curve. We will then determine the impact of the body effect on the dc voltage transfer curve and the logic levels. A transient analysis of the NMOS inverter will determine the propagation delay time in NMOS logic circuits. We will then develop and analyze basic NMOS NOR and NAND logic gates, as well as circuits that perform more complex logic functions. The CMOS inverter is the basic of CMOS logic gates. We will analyze the inverter dc voltage transfer characteristics, and will determine the power dissipation in the CMOS inverter, demonstrating the principle advantage of CMOS inverter over NMOS circuits. Next, we will develop the noise margin of the CMOS inverter, and then will develop and analyze basic CMOS NOR and NAND logic gates. Finally, we will look at more advanced clocked CMOS logic circuits which eliminate almost half of transistors in a conventional CMOS logic design while maintaining the low power advantage of the CMOS technology. In a digital system, a transistor can act as a switch between a driving circuit and a load circuit. An NMOS transistor that performs this function is called an NMOS transmission gate; the corresponding CMOS configuration is a CMOS transmission gate. These transmission gates, or pass transistors, can also be configured to perform logic functions, and the circuits are called NMOS-pass or CMOS-pass networks. We will discuss the basics of these networks. Finally in this module, we will consider a few examples of sequential logic circuits. Two dynamic shift registers are defined and analyzed, and a static R-S flip-flop are defined and analyzed.

This module presents the basic concepts of MOSFET digital logic circuits. We will examine NMOS logic circuits, which contain only n-channel transistors, and complementary MOS, or CMOS, logic circuits, which contain both n-channel and p-channel transistors. JFET logic circuits are very specialized and therefore not considered here.

The NMOS inverter is the basic of NMOS digital logic circuits. We will analyze the dc voltage transfer characteristics of several inverter designs. We will also define and develop the noise margin of NMOS digital circuits in terms of the inverter voltage transfer curve. We will then determine the impact of the body effect on the dc voltage transfer curve and the logic levels. A transient analysis of the NMOS inverter will determine the propagation delay time in NMOS logic circuits. We will then develop and analyze basic NMOS NOR and NAND logic gates, as well as circuits that perform more complex logic functions.

The CMOS inverter is the basic of CMOS logic gates. We will analyze the inverter dc voltage transfer characteristics, and will determine the power dissipation in the CMOS inverter, demonstrating the principle advantage of CMOS inverter over NMOS circuits. Next, we will develop the noise margin of the CMOS inverter, and then will develop and analyze basic CMOS NOR and NAND logic gates. Finally, we will look at more advanced clocked CMOS logic circuits which eliminate almost half of transistors in a conventional CMOS logic design while maintaining the low power advantage of the CMOS technology.

In a digital system, a transistor can act as a switch between a driving circuit and a load circuit. An NMOS transistor that performs this function is called an NMOS transmission gate; the corresponding CMOS configuration is a CMOS transmission gate. These transmission gates, or pass transistors, can also be configured to perform logic functions, and the circuits are called NMOS-pass or CMOS-pass networks. We will discuss the basics of these networks.

Finally in this module, we will consider a few examples of sequential logic circuits. Two dynamic shift registers are defined and analyzed, and a static R-S flip-flop are defined and analyzed.

NMOS INVERTERS

The inverter is the basic circuit of most MOS logic circuits. The design techniques used in NMOS logic circuits are developed from the dc analysis results for NMOS inverter. Extending the concepts developed from the inverter to NOR and NAND gates is then direct. Alternative inverter load elements are compared in terms of power consumption, packing density, and transfer characteristics. The transient analysis and switching characteristics of the inverters give an indication of the propagation delay times of NMOS logic circuits.

n-Channel MOSFET

In this section, we will quickly review the n-channel MOSFET characteristics, emphasizing specific properties important in digital circuit design.

A simplified n-channel MOSFET is shown in Figure 1. The body or substrate, is a single crystal silicon wafer which is the starting material for circuit fabrication and provides physical support for the integrated circuit. The active transistor region is the surface of the semiconductor and is comprised of the heavy doped n+n+ size 12{n rSup { size 8{+{}} } } {} source and drain regions and p-type channel region. The channel length is L and the channel width is W. normally, in any given fabrication process, the channel length is the same for all transistors, while the channel width is variable.

Figure 1: a) n-chanel MOSFET simplified view and b)n-channel MOSFET detailed cross section
Figure 1 (graphics1.png)

Figure 1b shows a more detailed view of the n-channel MOSFET. This figure demonstrates that the actual device geometry is more complicated than that indicated by the simplified cross section.

Figure 2: a) Simplified circuit symbols for n-channel MOSFETs and b) circuit symbols showing substrate or body terminal
Figure 2 (graphics2.png)

Figure 2a shows the simplified circuit symbols for the n-channel enhancement and depletion-mode devices. When we explicitly consider the body or substrate connection, we will use the symbols shows in Figure 2b.

In an integrated circuit, all n-channel transistors are fabricated in the same p-type substrate material. The substrate is connected to the most negative potential in the circuit, which for digital circuits, is normally at ground potential or zero volts. However, the source terminal of many of transistors will not be at zero volts, which means that a reverse-biased pn junction will exist between source and substrate.

When the source and body terminal are connected together, the threshold voltage, to a first approximation, is independent of the applied voltages. However, when the source and body voltages are not equal, as when transistors are used for active loads, for instance, the threshold voltage is a function of difference between these voltages. We can write

V Th = V Th 0 + 2eε s N a C ox [ 2φ fp + V SB − 2φ fp ] = V Th 0 + γ [ 2φ fp + V SB − 2φ fp ] V Th = V Th 0 + 2eε s N a C ox [ 2φ fp + V SB − 2φ fp ] = V Th 0 + γ [ 2φ fp + V SB − 2φ fp ] size 12{V rSub { size 8{ ital "Th"} } =V rSub { size 8{ ital "Th"0} } + { { sqrt {2eε rSub { size 8{s} } N rSub { size 8{a} } } } over {C rSub { size 8{ ital "ox"} } } } \[ sqrt {2φ rSub { size 8{ ital "fp"} } +V rSub { size 8{ ital "SB"} } } - sqrt {2φ rSub { size 8{ ital "fp"} } } \] =V rSub { size 8{ ital "Th"0} } +γ \[ sqrt {2φ rSub { size 8{ ital "fp"} } +V rSub { size 8{ ital "SB"} } } - sqrt {2φ rSub { size 8{ ital "fp"} } } \] } {} (1)

where VSBVSB size 12{V rSub { size 8{ ital "SB"} } } {} is the source-to-body voltage, and VTh0VTh0 size 12{V rSub { size 8{ ital "Th"0} } } {} is the threshold voltage for zero source-to-body voltage or VSB=0VSB=0 size 12{V rSub { size 8{ ital "SB"} } =0} {}. The parameter NaNa size 12{N rSub { size 8{a} } } {} is the p-type substrate doping concentration, εsεs size 12{ε rSub { size 8{s} } } {} is the semiconductor permittivity, CoxCox size 12{C rSub { size 8{ ital "ox"} } } {} is the oxide capacitance per unit area, φfpφfp size 12{φ rSub { size 8{ ital "fp"} } } {} is a potential related to the substrate doping concentration, and γγ size 12{γ} {} is the body-effect coefficient.

The current-voltage characteristics of the n-channel MOSFET are functions of both the electrical and geometrical properties of the device. When the transistor is biased in the nonsaturation region, for vGS≥VThvGS≥VTh size 12{v rSub { size 8{ ital "GS"} } >= V rSub { size 8{ ital "Th"} } } {} and vDS≤(vGS−VTh)vDS≤(vGS−VTh) size 12{v rSub { size 8{ ital "DS"} } <= \( v rSub { size 8{ ital "GS"} } - V rSub { size 8{ ital "Th"} } \) } {}, we can write

i D = k n [ 2 ( V GS − V Th ) v DS − v DS 2 ] i D = k n [ 2 ( V GS − V Th ) v DS − v DS 2 ] size 12{i rSub { size 8{D} } =k rSub { size 8{n} } \[ 2 \( V rSub { size 8{ ital "GS"} } - V rSub { size 8{ ital "Th"} } \) v rSub { size 8{ ital "DS"} } - v rSub { size 8{ ital "DS"} } rSup { size 8{2} } \] } {} (2)

In the saturation region, for vGS≥VThvGS≥VTh size 12{v rSub { size 8{ ital "GS"} } >= V rSub { size 8{ ital "Th"} } } {}, and vDS≥(vGS−VTh)vDS≥(vGS−VTh) size 12{v rSub { size 8{ ital "DS"} } >= \( v rSub { size 8{ ital "GS"} } - V rSub { size 8{ ital "Th"} } \) } {}, we have

i D = k n ( v GS − V Th ) 2 i D = k n ( v GS − V Th ) 2 size 12{i rSub { size 8{D} } =k rSub { size 8{n} } \( v rSub { size 8{ ital "GS"} } - V rSub { size 8{ ital "Th"} } \) rSup { size 8{2} } } {} (3)

The transition point separates the non-saturation and saturation regions and is the drain-to-source saturation voltage which is given by

v DS = v DS ( sat ) = v GS − V Th v DS = v DS ( sat ) = v GS − V Th size 12{v rSub { size 8{ ital "DS"} } =v rSub { size 8{ ital "DS"} } \( ital "sat" \) =v rSub { size 8{ ital "GS"} } - V rSub { size 8{ ital "Th"} } } {} (4)

The term (1+λvDS)(1+λvDS) size 12{ \( 1+λv rSub { size 8{ ital "DS"} } \) } {} is sometimes included in Equation 4b to account for channel length modulation and the finite output resistance. In most cases, it has little effect on the operating characteristics of MOS digital circuits. In our analysis, the term λλ size 12{λ} {} is assumed to be zero unless otherwise stated.

The parameter knkn size 12{k rSub { size 8{n} } } {} is the NMOS transistor conduction parameter and is given by

k n = ( 1 2 μ n C ox ) ( W L ) = k n ' 2 W L k n = ( 1 2 μ n C ox ) ( W L ) = k n ' 2 W L size 12{k rSub { size 8{n} } = \( { {1} over {2} } μ rSub { size 8{n} } C rSub { size 8{ ital "ox"} } \) \( { {W} over {L} } \) = { {k rSub { size 8{n} } rSup { size 8{'} } } over {2} } { {W} over {L} } } {} (5)

The electron mobility μnμn size 12{μ rSub { size 8{n} } } {} and oxide capacitance C0xC0x size 12{C rSub { size 8{0x} } } {} are assumed to be constant for all devices in a particular IC.

The current-voltage characteristics are directly related to the channel width-to-length ratio, or the size of the transistor. In general, in a given IC, the length L is fixed, but the designer can control the channel width W.

Since the MOS transistor is a majority carrier device, the switching speed of MOS digital circuits is limited by the time required to charge or discharge the capacitances between device electrodes and between interconnect lines and ground. Figure 3 shows the significant capacitances in a MOSFET. The capacitances CsbCsb size 12{C rSub { size 8{ ital "sb"} } } {} and CdbCdb size 12{C rSub { size 8{ ital "db"} } } {} are the source-to-body and drain-to-body n+n+ size 12{n rSup { size 8{+{}} } } {}p junction capacitances. The total input gate capacitance, to a first approximation, is a constant equal to

C g = WLC ox = WL ( ε ox t ox ) C g = WLC ox = WL ( ε ox t ox ) size 12{C rSub { size 8{g} } = ital "WLC" rSub { size 8{ ital "ox"} } = ital "WL" \( { {ε rSub { size 8{ ital "ox"} } } over {t rSub { size 8{ ital "ox"} } } } \) } {} (6)

where C0xC0x size 12{C rSub { size 8{0x} } } {} is the oxide capacitance per unit area, and is a function of the oxide thickness. The parameter C0xC0x size 12{C rSub { size 8{0x} } } {} also appears in the expression for the conduction parameter.

Figure 3: n-channel MOSFET and device capacitances
Figure 3 (graphics3.png)

NMOS Inverter Transfer Characteristics

Since the inverter is the basic for most logic circuits, we will describe the NMOS inverter and will develop the dc transfer characteristics for three types of inverters with different load devices. This discussion will introduce voltage transfer functions, noise margins, and the transient characteristics of FET digital circuits.

NMOS inverter with resistor load

Figure 4a shows a single NMOS transistor connected to a resistor to form an inverter. The transistor characteristics and load line are shown in Figure 4b, along with the parametric curve separating the saturation and nonsaturation regions. We determine the voltage transfer characteristics of the inverter by examining the various regions in which the transistor can be biased.

Figure 4: a) NMOS inverter with resistor load and b) transistor characteristics and load line
Figure 4 (graphics4.png)

When the input voltage is less than or equal to the threshold, or vI≤VThvI≤VTh size 12{v rSub { size 8{I} } <= V rSub { size 8{ ital "Th"} } } {}, the transistor is cut off, iD=0iD=0 size 12{i rSub { size 8{D} } =0} {}, and the output voltage is v0=VDDv0=VDD size 12{v rSub { size 8{0} } =V rSub { size 8{ ital "DD"} } } {}. The maximum output voltage is defined as the logic 1 level. As the input voltage becomes just greater than VThVTh size 12{V rSub { size 8{ ital "Th"} } } {}, the transistor turns on and is biased in the saturation region. The output voltage is than

v 0 = V DD − i D R D v 0 = V DD − i D R D size 12{v rSub { size 8{0} } =V rSub { size 8{ ital "DD"} } - i rSub { size 8{D} } R rSub { size 8{D} } } {} (7)

Where the drain current is given by

i D = k n ( v GS − V Th ) 2 = k n ( v I − V Th ) 2 i D = k n ( v GS − V Th ) 2 = k n ( v I − V Th ) 2 size 12{i rSub { size 8{D} } =k rSub { size 8{n} } \( v rSub { size 8{ ital "GS"} } - V rSub { size 8{ ital "Th"} } \) rSup { size 8{2} } =k rSub { size 8{n} } \( v rSub { size 8{I} } - V rSub { size 8{ ital "Th"} } \) rSup { size 8{2} } } {} (8)

Combining Equation 7 and (Reference) yields

v 0 = V DD − k n R D ( v I − V Th ) 2 v 0 = V DD − k n R D ( v I − V Th ) 2 size 12{v rSub { size 8{0} } =V rSub { size 8{ ital "DD"} } - k rSub { size 8{n} } R rSub { size 8{D} } \( v rSub { size 8{I} } - V rSub { size 8{ ital "Th"} } \) rSup { size 8{2} } } {} (9)

which relates the output and input voltages as long as the transistor is biased in the saturation region.

As the input voltage increases, the Q-point of the transistor moves up the load line. At the transition point, we have

V 0t = V It − V Th V 0t = V It − V Th size 12{V rSub { size 8{0t} } =V rSub { size 8{ ital "It"} } - V rSub { size 8{ ital "Th"} } } {} (10)

where V0tV0t size 12{V rSub { size 8{0t} } } {} and VItVIt size 12{V rSub { size 8{ ital "It"} } } {} are the drain-to-source and gate-to-source voltage, respectively, at the transition point. Substituting Equation 10 into Equation 9, the input voltage at the transition point is the determined from

K n R D ( V It − V Th ) 2 + ( V D − V Th ) − V DD = 0 K n R D ( V It − V Th ) 2 + ( V D − V Th ) − V DD = 0 size 12{K rSub { size 8{n} } R rSub { size 8{D} } \( V rSub { size 8{ ital "It"} } - V rSub { size 8{ ital "Th"} } \) rSup { size 8{2} } + \( V rSub { size 8{D} } - V rSub { size 8{ ital "Th"} } \) - V rSub { size 8{ ital "DD"} } =0} {} (11)

As the input voltage becomes greater than VItVIt size 12{V rSub { size 8{ ital "It"} } } {}, the Q-point continues to move up the load line, and the transistor becomes biased in the nonsaturation region. The drain current is then

i D = k n 2 ( v GS − V Th ) v DS − v DS 2 = k n 2 ( v I − V Th ) v 0 − v 0 2 i D = k n 2 ( v GS − V Th ) v DS − v DS 2 = k n 2 ( v I − V Th ) v 0 − v 0 2 size 12{i rSub { size 8{D} } =k rSub { size 8{n} } left [2 \( v rSub { size 8{ ital "GS"} } - V rSub { size 8{ ital "Th"} } \) v rSub { size 8{ ital "DS"} } - v rSub { size 8{ ital "DS"} } rSup { size 8{2} } right ]=k rSub { size 8{n} } left [2 \( v rSub { size 8{I} } - V rSub { size 8{ ital "Th"} } \) v"" lSub { size 8{0} } - v rSub { size 8{0} } rSup { size 8{2} } right ]} {} (12)

Combining Equation 7 and Equation 12 yields

v 0 = V DD − k n R D [ 2 ( v I − V Th ) v 0 − v 0 2 ] v 0 = V DD − k n R D [ 2 ( v I − V Th ) v 0 − v 0 2 ] size 12{v rSub { size 8{0} } =V rSub { size 8{ ital "DD"} } - k rSub { size 8{n} } R rSub { size 8{D} } \[ 2 \( v rSub { size 8{I} } - V rSub { size 8{ ital "Th"} } \) v"" lSub { size 8{0} } - v rSub { size 8{0} } rSup { size 8{2} } \] } {} (13)

Which relates to the input and output voltage as long as the transistor is biased in the nonsaturation region.

Figure 5 shows the voltage transfer characteristics of this inverter for three resistor values. Also shown is the line, given by Equation 10, which separates the saturation and nonsaturation bias region of the transistor. The figure shows that the minimum output voltage, or the logic 0 level, for a high input decreases with increasing load resistance, and the sharpness of the transition region between a low input and a high input increases with increasing load resistance.

Figure 5: Voltage transfer characteristics, NMOS inverter with resistor load, for three resistor values
Figure 5 (graphics5.png)

It should be note that a large resistance is difficult to fabricate in an IC. A large resistor value in the inverter will limit current and power consumption as well as provide a small VOLVOL size 12{V rSub { size 8{ ital "OL"} } } {} value. But it would also require a large chip area if fabricated in a standard MOS process. To avoid this problem, MOS transistors can be used as load devices, replacing the resistor, as discussed in subsequent paragraphs.

NMOS inverter with enhancement load

An n-channel enhancement-mode MOSFET with the gate connected to the drain can be used as a load device in an NMOS inverter. Figure 6a shows such a device. For vGS=vDS≤VThvGS=vDS≤VTh size 12{v rSub { size 8{ ital "GS"} } =v rSub { size 8{ ital "DS"} } <= V rSub { size 8{ ital "Th"} } } {}, the drain current is zero. For vGS=vDS≥VThvGS=vDS≥VTh size 12{v rSub { size 8{ ital "GS"} } =v rSub { size 8{ ital "DS"} } >= V rSub { size 8{ ital "Th"} } } {}, a nonzero drain current is induced in the device. We can see that the following condition is satisfied:

v DS > ( v GS − V Th ) = ( v DS − V Th ) = v DS ( sat ) v DS > ( v GS − V Th ) = ( v DS − V Th ) = v DS ( sat ) size 12{v rSub { size 8{ ital "DS"} } > \( v rSub { size 8{ ital "GS"} } - V rSub { size 8{ ital "Th"} } \) = \( v rSub { size 8{ ital "DS"} } - V rSub { size 8{ ital "Th"} } \) =v rSub { size 8{ ital "DS"} } \( ital "sat" \) } {} (14)

A transistor with this connection always operates in the saturation region when not in cutoff.

The drain current is

i D = k n ( v GS − V Th ) 2 = k n ( v DS − V Th ) 2 i D = k n ( v GS − V Th ) 2 = k n ( v DS − V Th ) 2 size 12{i rSub { size 8{D} } =k rSub { size 8{n} } \( v rSub { size 8{ ital "GS"} } - V rSub { size 8{ ital "Th"} } \) rSup { size 8{2} } =k rSub { size 8{n} } \( v rSub { size 8{ ital "DS"} } - V rSub { size 8{ ital "Th"} } \) rSup { size 8{2} } } {} (15)

We continue to neglect the effect of the output resistance and the λλ size 12{λ} {} parameter. The iDiD size 12{i rSub { size 8{D} } } {} versus vDCvDC size 12{v rSub { size 8{ ital "DC"} } } {} characteristic is shown in Figure 7b which indicates that this device acts as a nonlinear resistor.

Figure 6: a) n-channel MOSFET connected as saturated load device and b) current-voltage characteristics of saturated load device
Figure 6 (graphics6.png)

Figure 7a shows an NMOS inverter with the enhancement load device. The driver transistor parameters are denoted by VThLVThL size 12{V rSub { size 8{ ital "ThL"} } } {} and kLkL size 12{k rSub { size 8{L} } } {}. The substrate connections are not shown. In the following analysis, we neglect the body effect and we assume all threshold voltages are constant. These assumptions do not seriously affect the basic analysis or the inverter characteristics.

The driver transistor characteristics and the load curve are shown in Figure 7b. When the inverter input voltage is less than the driver threshold voltage, the driver is cut off and the drain currents are zero. From Equation 15, we have

i DL = 0 = k L ( v DSL − V ThL ) 2 i DL = 0 = k L ( v DSL − V ThL ) 2 size 12{i rSub { size 8{ ital "DL"} } =0=k rSub { size 8{L} } \( v rSub { size 8{ ital "DSL"} } - V rSub { size 8{ ital "ThL"} } \) rSup { size 8{2} } } {} (16)

From Figure 7a, we see that vDSL=VDD−v0vDSL=VDD−v0 size 12{v rSub { size 8{ ital "DSL"} } =V rSub { size 8{ ital "DD"} } - v rSub { size 8{0} } } {}, which means that

v DSL − V ThL = V DD − v 0 − V ThL = 0 v DSL − V ThL = V DD − v 0 − V ThL = 0 size 12{v rSub { size 8{ ital "DSL"} } - V rSub { size 8{ ital "ThL"} } =V rSub { size 8{ ital "DD"} } - v rSub { size 8{0} } - V rSub { size 8{ ital "ThL"} } =0} {} (17)

The maximum output voltage is then

V 0 max = V OH = V DD − V ThL V 0 max = V OH = V DD − V ThL size 12{V rSub { size 8{0"max"} } =V rSub { size 8{ ital "OH"} } =V rSub { size 8{ ital "DD"} } - V rSub { size 8{ ital "ThL"} } } {} (18)

For the enhancement load NMOS inverter, the maximum output voltage, which is the logic 1 level, does not reach the full VDDVDD size 12{V rSub { size 8{ ital "DD"} } } {} value. This cutoff point is shown on the load curve in Figure 7b.

Figure 7: a) NMOS inverter with saturated load and b) driver transistor characteristics and load curve
Figure 7 (graphics7.png)

As the input voltage becomes just greater than the driver threshold voltage VThDVThD size 12{V rSub { size 8{ ital "ThD"} } } {}, the driver transistor turns on and is biased in the saturation region. In steady-state, the two drain currents are equal since the output will be connected to the gates of other MOS transistors. We have iDD=iDLiDD=iDL size 12{i rSub { size 8{ ital "DD"} } =i rSub { size 8{ ital "DL"} } } {}, which can be written as

k D ( v GSD − V ThD ) 2 = k L ( v GSL − V ThL ) 2 k D ( v GSD − V ThD ) 2 = k L ( v GSL − V ThL ) 2 size 12{k rSub { size 8{D} } \( v rSub { size 8{ ital "GSD"} } - V rSub { size 8{ ital "ThD"} } \) rSup { size 8{2} } =k rSub { size 8{L} } \( v rSub { size 8{ ital "GSL"} } - V rSub { size 8{ ital "ThL"} } \) rSup { size 8{2} } } {} (19)

Equation 20 is expressed in terms of the individual transistor parameters. In terms of the input and output voltages, the expression becomes

k D ( v I − V ThD ) 2 = k L ( V DD − v 0 − V ThL ) 2 k D ( v I − V ThD ) 2 = k L ( V DD − v 0 − V ThL ) 2 size 12{k rSub { size 8{D} } \( v rSub { size 8{I} } - V rSub { size 8{ ital "ThD"} } \) rSup { size 8{2} } =k rSub { size 8{L} } \( V rSub { size 8{ ital "DD"} } - v rSub { size 8{0} } - V rSub { size 8{ ital "ThL"} } \) rSup { size 8{2} } } {} (20)

Solving for the output voltage yields

v 0 = V DD − V ThL − k D k L v I − V ThD v 0 = V DD − V ThL − k D k L v I − V ThD size 12{v rSub { size 8{0} } =V rSub { size 8{ ital "DD"} } - V rSub { size 8{ ital "ThL"} } - sqrt { { {k rSub { size 8{D} } } over {k rSub { size 8{L} } } } } left (v rSub { size 8{I} } - V rSub { size 8{ ital "ThD"} } right )} {} (21)

As the input voltage increases, the driver Q-point moves up the load curve and the output voltage deceases linearly with vIvI size 12{v rSub { size 8{I} } } {}.

At the driver transition point, we have

v DSD ( sat ) = v GSD − V ThD v DSD ( sat ) = v GSD − V ThD size 12{v rSub { size 8{ ital "DSD"} } \( ital "sat" \) =v rSub { size 8{ ital "GSD"} } - V rSub { size 8{ ital "ThD"} } } {}

v DSD ( sat ) = v GSD − V ThD v DSD ( sat ) = v GSD − V ThD size 12{v rSub { size 8{ ital "DSD"} } \( ital "sat" \) =v rSub { size 8{ ital "GSD"} } - V rSub { size 8{ ital "ThD"} } } {} (22)

or

v 0t = v It − V ThD v 0t = v It − V ThD size 12{v rSub { size 8{0t} } =v rSub { size 8{ ital "It"} } - V rSub { size 8{ ital "ThD"} } } {} (23)

Substituting Equation 23 into Equation 21, we find the input voltage at the transition point, which is

V It = V DD − V ThL + V ThD ( 1 + k D k L ) 1 + k D k L V It = V DD − V ThL + V ThD ( 1 + k D k L ) 1 + k D k L size 12{V rSub { size 8{ ital "It"} } = { {V rSub { size 8{ ital "DD"} } - V rSub { size 8{ ital "ThL"} } +V rSub { size 8{ ital "ThD"} } \( 1+ sqrt { { {k rSub { size 8{D} } } over {k rSub { size 8{L} } } } } \) } over {1+ sqrt { { {k rSub { size 8{D} } } over {k rSub { size 8{L} } } } } } } } {} (24)

As the input voltage becomes greater than VItVIt size 12{V rSub { size 8{ ital "It"} } } {}, the driver transistor Q-point continues to move up the load curve and the driver becomes biased in the nonsaturation region. Since the driver and load drain currents are still equal, or iDD=iDLiDD=iDL size 12{i rSub { size 8{ ital "DD"} } =i rSub { size 8{ ital "DL"} } } {}, we now have

k D [ 2 ( v GSD − V ThD ) v DSD − v DSD 2 ] = k L ( v DSL − V ThL ) 2 k D [ 2 ( v GSD − V ThD ) v DSD − v DSD 2 ] = k L ( v DSL − V ThL ) 2 size 12{k rSub { size 8{D} } \[ 2 \( v rSub { size 8{ ital "GSD"} } - V rSub { size 8{ ital "ThD"} } \) v rSub { size 8{ ital "DSD"} } - v rSub { size 8{ ital "DSD"} } rSup { size 8{2} } \] =k rSub { size 8{L} } \( v rSub { size 8{ ital "DSL"} } - V rSub { size 8{ ital "ThL"} } \) rSup { size 8{2} } } {} (25)

Writing Equation 25 in terms of the input and output voltages produces

k D [ 2 ( v I − V ThD ) v 0 − v 0 2 ] = k L ( V DD − v 0 − V ThL ) 2 k D [ 2 ( v I − V ThD ) v 0 − v 0 2 ] = k L ( V DD − v 0 − V ThL ) 2 size 12{k rSub { size 8{D} } \[ 2 \( v rSub { size 8{I} } - V rSub { size 8{ ital "ThD"} } \) v rSub { size 8{0} } - v rSub { size 8{0} } rSup { size 8{2} } \] =k rSub { size 8{L} } \( V rSub { size 8{ ital "DD"} } - v rSub { size 8{0} } - V rSub { size 8{ ital "ThL"} } \) rSup { size 8{2} } } {} (26)

Obviously, the relationship between v1v1 size 12{v rSub { size 8{1} } } {} and v0v0 size 12{v rSub { size 8{0} } } {} in this region is not linear.

Figure 8 shows the voltage transfer characteristics of this inverter for three kDkD size 12{k rSub { size 8{D} } } {}-to- kLkL size 12{k rSub { size 8{L} } } {} ratios. The ratio kD/kLkD/kL size 12{ {k rSub { size 8{D} } } slash {k rSub { size 8{L} } } } {} is the aspect ratio and is related to the width-to-length parameters of the driver and load transistors.

The line, given by Equation 23, separating the driver saturation and nonsaturation regions is also shown in the figure. We see that the minimum output voltage, or the logic 0 level, for a high input decreases with an increasing kD/kLkD/kL size 12{ {k rSub { size 8{D} } } slash {k rSub { size 8{L} } } } {} ratio. As the width-to-length ratio of the load transistor decreases, the effective resistance increases, which means that the general behavior of the transfer characteristics is the same as for the resistor load. However, the high output voltage is

V OH = V DD − V ThL V OH = V DD − V ThL size 12{V rSub { size 8{ ital "OH"} } =V rSub { size 8{ ital "DD"} } - V rSub { size 8{ ital "ThL"} } } {}

When the driver is biased in the saturation region, we find the slope of the transfer curve, which is the inverter gain, by taking the derivative of Equation 21 with respect to vIvI size 12{v rSub { size 8{I} } } {}. We see that

dv 0 / dv I = − k D / k L dv 0 / dv I = − k D / k L size 12{ ital "dv" rSub { size 8{0} } / ital "dv" rSub { size 8{I} } = - sqrt {k rSub { size 8{D} } /k rSub { size 8{L} } } } {}

When the aspect ratio is greater than unity, the inverter gain magnitude is greater than unity. A logic circuit family with an inverter transfer curve that exhibits a gain greater than unity for some region is called a restoring logic family. Restoring logic is so named because logic signals that are degraded for some reason in one circuit can be restored by gain of subsequent logic circuits.

Figure 8: Voltage transfer characteristics, NMOS inverter with saturated load, for three aspect ratios
Figure 8 (graphics8.png)

NMOS inverter with depletion load

Depletion mode MOSFET can also be used as load elements in NMOS inverters. Figure 9a shows the NMOS inverter with depletion load. The gate and source of the depletion mode transistor are connected together. The driver transistor is still an enhancement-mode device. As before, the driver transistor parameters are VThDVThD size 12{V rSub { size 8{ ital "ThD"} } } {} ( VThDVThD size 12{V rSub { size 8{ ital "ThD"} } } {}> 0) and kDkD size 12{k rSub { size 8{D} } } {}, and the load transistor parameters are VThLVThL size 12{V rSub { size 8{ ital "ThL"} } } {} ( VThLVThL size 12{V rSub { size 8{ ital "ThL"} } } {}< 0) and kLkL size 12{k rSub { size 8{L} } } {}. Again, the substrate connections are not shown. The fabrication process for this inverter is slightly more complicated than for the enhancement-load inverter, since the threshold voltages of the two devices are not equal. However, as we will see, the advantage of the inverter makes the extra processing steps worthwhile. This inverter has been the basic of many microprocessor and static memory designs.

Figure 9: a) NMOS inverter with depletion load, b) current-voltage characteristic of depletion load, and c) driver transistor characteristics and load curve
Figure 9 (graphics9.png)

The current-voltage characteristic curve for the depletion load, neglecting the body effect, is shown in Figure 9b. Since the gate is connected to the source, vGSL=0vGSL=0 size 12{v rSub { size 8{ ital "GSL"} } =0} {}, and the Q-point of the load is on this particular curve.

The driver transistor characteristics and the ideal load curve are shown in (Reference)c. When the inverter input is less than the driver threshold voltage, the driver is cut off and the drain currents are zero. From Figure 9b, we see that for vD=0vD=0 size 12{v rSub { size 8{D} } =0} {}, the drain-to-source voltage of the load transistor must be zero; therefore, v0=VDDv0=VDD size 12{v rSub { size 8{0} } =V rSub { size 8{ ital "DD"} } } {} for vI≤VThDvI≤VThD size 12{v rSub { size 8{I} } <= V rSub { size 8{ ital "ThD"} } } {}. An advantage of the depletion load inverter over the enhancement-load inverter is that the high output voltage, or the logic 1 level, is at the full VDDVDD size 12{V rSub { size 8{ ital "DD"} } } {} value.

As the input voltage becomes just greater than the driver threshold voltage VThDVThD size 12{V rSub { size 8{ ital "ThD"} } } {}, the driver turns on and is biased in the saturation region; however, the load is biased in the nonsaturation region. The Q-point lies between points A and B on the load curve shown in Figure 9c. We again set the two drain currents equal, or iDD=iDLiDD=iDL size 12{i rSub { size 8{ ital "DD"} } =i rSub { size 8{ ital "DL"} } } {}, which means that

k D v GSD − V ThD 2 = k L 2 ( v GSL − V ThL ) v DSL − v DSL 2 k D v GSD − V ThD 2 = k L 2 ( v GSL − V ThL ) v DSL − v DSL 2 size 12{k rSub { size 8{D} } left [v rSub { size 8{ ital "GSD"} } - V rSub { size 8{ ital "ThD"} } right ] rSup { size 8{2} } =k rSub { size 8{L} } left [2 \( v rSub { size 8{ ital "GSL"} } - V rSub { size 8{ ital "ThL"} } \) v rSub { size 8{ ital "DSL"} } - v rSub { size 8{ ital "DSL"} } rSup { size 8{2} } right ]} {} (27)

Writing Equation 27 in terms of the input and output voltages yields

k D v I − V ThD 2 = k L 2 ( − V ThL ) ( V DD − v 0 ) − ( V DD − v 0 ) 2 k D v I − V ThD 2 = k L 2 ( − V ThL ) ( V DD − v 0 ) − ( V DD − v 0 ) 2 size 12{k rSub { size 8{D} } left [v rSub { size 8{I} } - V rSub { size 8{ ital "ThD"} } right ] rSup { size 8{2} } =k rSub { size 8{L} } left [2 \( - V rSub { size 8{ ital "ThL"} } \) \( V rSub { size 8{ ital "DD"} } - v rSub { size 8{0} } \) - \( V rSub { size 8{ ital "DD"} } - v rSub { size 8{0} } \) rSup { size 8{2} } right ]} {} (28)

This equation relates the input and output voltages as long as the driver is biased in saturation region and the load is biased in the nonsaturation region.

There are two transition points for the NMOS inverter with a depletion load: one for the load and one for the driver. These are points B and C, respectively, in Figure 9c. The transition point for load is given by

v DSL = V DD − V 0t = v GSL − V ThL = − V ThL v DSL = V DD − V 0t = v GSL − V ThL = − V ThL size 12{v rSub { size 8{ ital "DSL"} } =V rSub { size 8{ ital "DD"} } - V rSub { size 8{0t} } =v rSub { size 8{ ital "GSL"} } - V rSub { size 8{ ital "ThL"} } = - V rSub { size 8{ ital "ThL"} } } {} (29)

or

V 0t = V DD + V ThL V 0t = V DD + V ThL size 12{V rSub { size 8{0t} } =V rSub { size 8{ ital "DD"} } +V rSub { size 8{ ital "ThL"} } } {} (30)

Since VThLVThL size 12{V rSub { size 8{ ital "ThL"} } } {} is negative, the output voltage at the transition point is less than VDDVDD size 12{V rSub { size 8{ ital "DD"} } } {}. The transition point for the driver is given by

V 0t = V It + V ThL V 0t = V It + V ThL size 12{V rSub { size 8{0t} } =V rSub { size 8{ ital "It"} } +V rSub { size 8{ ital "ThL"} } } {} (31)

When the Q-point lies between points B and C on the load curve, both devices are biased in the saturation region, and

k D ( v GSD − V ThD ) 2 = k L ( v GSL − V ThL ) 2 k D ( v GSD − V ThD ) 2 = k L ( v GSL − V ThL ) 2 size 12{k rSub { size 8{D} } \( v rSub { size 8{ ital "GSD"} } - V rSub { size 8{ ital "ThD"} } \) rSup { size 8{2} } =k rSub { size 8{L} } \( v rSub { size 8{ ital "GSL"} } - V rSub { size 8{ ital "ThL"} } \) rSup { size 8{2} } } {} (32)

or

k D k L ( v I − V ThD ) = − V ThL k D k L ( v I − V ThD ) = − V ThL size 12{ sqrt { { {k rSub { size 8{D} } } over {k rSub { size 8{L} } } } } \( v rSub { size 8{I} } - V rSub { size 8{ ital "ThD"} } \) = - V rSub { size 8{ ital "ThL"} } } {} (33)

Equation 33 demonstrates that the input voltage is a constant as the Q-point passes through this region. This effect is also shown in (Reference)c; the load curve between points B and C lies on a constant vGSDvGSD size 12{v rSub { size 8{ ital "GSD"} } } {} curve.

For an input voltage greater than the value given by Equation 33, the driver is biased in the nonsaturation region while the load is biased in the saturation region. The Q-point is now between points C and D on the load curve shown in Figure 9c. Equaing the two drain currents, we obtain

k D 2 ( v GSD − V ThD ) v DSD − v DSD 2 = k L ( v GSL − V ThL ) 2 k D 2 ( v GSD − V ThD ) v DSD − v DSD 2 = k L ( v GSL − V ThL ) 2 size 12{k rSub { size 8{D} } left [2 \( v rSub { size 8{ ital "GSD"} } - V rSub { size 8{ ital "ThD"} } \) v rSub { size 8{ ital "DSD"} } - v rSub { size 8{ ital "DSD"} } rSup { size 8{2} } right ]=k rSub { size 8{L} } \( v rSub { size 8{ ital "GSL"} } - V rSub { size 8{ ital "ThL"} } \) rSup { size 8{2} } } {} (34)

which becomes

k D k L 2 ( v I − V ThD ) v 0 − v 0 2 = ( − V ThL ) 2 k D k L 2 ( v I − V ThD ) v 0 − v 0 2 = ( − V ThL ) 2 size 12{ { {k rSub { size 8{D} } } over {k rSub { size 8{L} } } } left [2 \( v rSub { size 8{I} } - V rSub { size 8{ ital "ThD"} } \) v rSub { size 8{0} } - v rSub { size 8{0} } rSup { size 8{2} } right ]= \( - V rSub { size 8{ ital "ThL"} } \) rSup { size 8{2} } } {} (35)

This equation implies that the relationship between the input and output voltages is not linear in this region.

Figure 10 shows the voltage transfer characteristics of this inverter for three values of kD/kLkD/kL size 12{ {k rSub { size 8{D} } } slash {k rSub { size 8{L} } } } {}. Also shown are the loci of transition points for the load and driver transistor as given by (Reference) and Equation 31, respectively.

Figure 10: Voltage transfer characteristics, NMOS inverter with depletion load, for three aspect ratios
Figure 10 (graphics10.png)

CMOS INVERTER

Complementary MOS, or CMOS, circuits contain both n-channel and p-channel MOSFETs. As we will see, the power dissipation in CMOS logic circuits is much smaller than in NMOS circuits, which makes CMOS very attractive. We will briefly review the characteristics of p-channel transistors, and will then analyze the CMOS inverter, which is the basic of most CMOS logic circuits. We will examine the CMOS NOR and NAND gates and other basic CMOS logic circuits, covering power dissipation, noise margin, fanout, and switching characteristics.

p-Channel MOSFET

Figure 11 shows a simplified view of p-channel device. Again, the channel length is L and the channel width is W. Usually in any given fabrication process, the channel length is the same for all devices, so the channel width W is the variable in logic circuit design.

Figure 11: Simplified cross section of p-channel MOSFET
Figure 11 (graphics11.png)

Figure 12a shows the simplified circuit symbol for the p-channel enhancement-mode device. When the body or substrate connection is needed, we will use the symbol shown in Figure 12b. Usually, the p-channel depletion-mode device is not used in CMOS digital circuits; therefore, it is not addressed here.

Figure 12: a) Siplified circuit symbol, p-channel enhancement-mode MOSFET and b) circuit symbol showing substrate connection
Figure 12 (graphics12.png)

Normally, in an integrated circuit, more than one p-channel device will be fabricated in the same n-substrate so the p-channel transistors will exhibit a body effect. The n-substrate is connected to the most positive potential. The source terminal may be negative with respect to the substrate, therefore, voltage VBS may exist between the body and the source. The threshold voltage is

V Th = V Th 0 − 2eε s N d C ox [ 2φ fn + V BS − 2φ fn ] = V Th 0 − γ [ 2φ fn + V BS − 2φ fn ] V Th = V Th 0 − 2eε s N d C ox [ 2φ fn + V BS − 2φ fn ] = V Th 0 − γ [ 2φ fn + V BS − 2φ fn ] size 12{V rSub { size 8{ ital "Th"} } =V rSub { size 8{ ital "Th"0} } - { { sqrt {2eε rSub { size 8{s} } N rSub { size 8{d} } } } over {C rSub { size 8{ ital "ox"} } } } \[ sqrt {2φ rSub { size 8{ ital "fn"} } +V rSub { size 8{ ital "BS"} } } - sqrt {2φ rSub { size 8{ ital "fn"} } } \] =V rSub { size 8{ ital "Th"0} } - γ \[ sqrt {2φ rSub { size 8{ ital "fn"} } +V rSub { size 8{ ital "BS"} } } - sqrt {2φ rSub { size 8{ ital "fn"} } } \] } {} (36)

where VTh0VTh0 size 12{V rSub { size 8{ ital "Th"0} } } {} is the threshold voltage for zero body-to-source voltage, or VBS=0VBS=0 size 12{V rSub { size 8{ ital "BS"} } =0} {}. The parameter NdNd size 12{N rSub { size 8{d} } } {} is the n-substrate doping concentration and φfnφfn size 12{φ rSub { size 8{ ital "fn"} } } {} is the potential related to the substrate doping. The parameter γγ size 12{γ} {} is the body effect coefficient.

The current-voltage characteristics of the p-channel MOSFET are functions of both the electrical and geometric properties of the device. When the transistor is biased in the nonsaturation region; we have vSD≤vSG+VThvSD≤vSG+VTh size 12{v rSub { size 8{ ital "SD"} } <= v rSub { size 8{ ital "SG"} } +V rSub { size 8{ ital "Th"} } } {}. Therefore,

i D = k p 2 ( v SG + V Th ) v SD − v SD 2 i D = k p 2 ( v SG + V Th ) v SD − v SD 2 size 12{i rSub { size 8{D} } =k rSub { size 8{p} } left [2 \( v rSub { size 8{ ital "SG"} } +V rSub { size 8{ ital "Th"} } \) v rSub { size 8{ ital "SD"} } - v rSub { size 8{ ital "SD"} } rSup { size 8{2} } right ]} {} (37)

In the saturation region, we have vSD≥vSG+VThvSD≥vSG+VTh size 12{v rSub { size 8{ ital "SD"} } >= v rSub { size 8{ ital "SG"} } +V rSub { size 8{ ital "Th"} } } {}, which means that

i D = k p ( v SG + V Th ) 2 i D = k p ( v SG + V Th ) 2 size 12{i rSub { size 8{D} } =k rSub { size 8{p} } \( v rSub { size 8{ ital "SG"} } +V rSub { size 8{ ital "Th"} } \) rSup { size 8{2} } } {} (38)

The gate potential is negative with respect to the source. For the p-channel transistor to conduct, we must have vGS<VThvGS<VTh size 12{v rSub { size 8{ ital "GS"} } <V rSub { size 8{ ital "Th"} } } {}, where VThVTh size 12{V rSub { size 8{ ital "Th"} } } {} is negative for an enhancement-mode device. We also see that vSG>∣VTh∣vSG>∣VTh∣ size 12{v rSub { size 8{ ital "SG"} } > lline V rSub { size 8{ ital "Th"} } rline } {} when the p-channel device is conducting.

In most cases, the channel length modulation factor λλ size 12{λ} {} has very little effect on the operating characteristics of MOS digital circuits. Therefore, the term λλ size 12{λ} {} is assumed to be zero unless otherwise stated.

The transition point, which separates the nonsaturation and saturation bias region, is given by

v SD = v SD ( sat ) = v SG + V Th v SD = v SD ( sat ) = v SG + V Th size 12{v rSub { size 8{ ital "SD"} } =v rSub { size 8{ ital "SD"} } \( ital "sat" \) =v rSub { size 8{ ital "SG"} } +V rSub { size 8{ ital "Th"} } } {} (39)

The parameter kPkP size 12{k rSub { size 8{P} } } {} is the conduction parameter and given by

k P = ( 1 2 μ P C ox ) ( W L ) = k P ' 2 W L k P = ( 1 2 μ P C ox ) ( W L ) = k P ' 2 W L size 12{k rSub { size 8{P} } = \( { {1} over {2} } μ rSub { size 8{P} } C rSub { size 8{ ital "ox"} } \) \( { {W} over {L} } \) = { {k rSub { size 8{P} } rSup { size 8{'} } } over {2} } { {W} over {L} } } {} (40)

As before, the hole mobility μPμP size 12{μ rSub { size 8{P} } } {} and oxide capacitance C0xC0x size 12{C rSub { size 8{0x} } } {} are assumed to be constant for all devices. The hole mobility in p-channel silicon MOSFETs is approximately one-half the electron mobility μNμN size 12{μ rSub { size 8{N} } } {} in n-channel silicon MOSFETs. This means that a p-channel device must be approximately twice as large as that of an n-channel device in order that the two devices be electrically equivalent (that is, that they have the same conduction parameter values).

DC Analysis of the CMOS Inverter

The CMOS inverter, shown in (Reference), is a series combination of a p-channel and an n-channel MOSFET. The gates of the two MOSFETs are connected together to form the input and the two drains are connected together to form the output. Both transistors are enhancement-mode devices. The parameters of the NMOS are denoted by kNkN size 12{k"" lSub { size 8{N} } } {} and VThNVThN size 12{V rSub { size 8{ ital "ThN"} } } {}, where VThNVThN size 12{V rSub { size 8{ ital "ThN"} } } {}> 0, and the parameters of the PMOS are denoted by kPkP size 12{k rSub { size 8{P} } } {} and VThPVThP size 12{V rSub { size 8{ ital "ThP"} } } {}, where VThPVThP size 12{V rSub { size 8{ ital "ThP"} } } {}< 0.

Figure 13: CMOS inverter
Figure 13 (graphics13.png)

Figure 14 shows a simplified cross section of a CMOS inverter. In this process, a separate p-well region is formed within the starting n-substrate. The n-channel device is fabricated in the p-well region and the p-channel device is fabricated in n-substrate. Although other approaches, such as an n-well in a p-substrate, are also used to fabricate CMOS circuits, the important point is that the processing is more complicated for CMOS circuits than for NMOS circuits. However, the advantages of CMOS digital logic circuits over NMOS circuits justify their use.

Figure 14: Simplified cross section, CMOS inverter
Figure 14 (graphics14.png)

Voltage Transfer Curve

Figure 15 shows the transistor characteristics for both the n- and p-channel devices. We can determine the voltage transfer characteristics of the inverter by evaluating the various transistor bias regions. For vI=0vI=0 size 12{v rSub { size 8{I} } =0} {}, the NMOS device is cut off, iDN=0iDN=0 size 12{i rSub { size 8{ ital "DN"} } =0} {}, and iDP=0iDP=0 size 12{i rSub { size 8{ ital "DP"} } =0} {}. The PMOS source-to-gate voltage is VDDVDD size 12{V rSub { size 8{ ital "DD"} } } {} which means that the PMOS is biased on the curve marked B in Figure 15b. Since the only point on the curve corresponding to iDP=0iDP=0 size 12{i rSub { size 8{ ital "DP"} } =0} {} occurs at vSDP=0=VDD−v0vSDP=0=VDD−v0 size 12{v rSub { size 8{ ital "SDP"} } =0=V rSub { size 8{ ital "DD"} } - v rSub { size 8{0} } } {}, the output voltage is v0=VDDv0=VDD size 12{v rSub { size 8{0} } =V rSub { size 8{ ital "DD"} } } {}. This condition exists as long as the NMOS transistor is cut off, or vI=VThNvI=VThN size 12{v rSub { size 8{I} } =V rSub { size 8{ ital "ThN"} } } {}.

Figure 15: Current-voltage characteristics, a) NMOS transistor and b) PMOS transistor
Figure 15 (graphics15.png)

For vI=VDDvI=VDD size 12{v rSub { size 8{I} } =V rSub { size 8{ ital "DD"} } } {}, the PMOS device is cut off, iDP=0iDP=0 size 12{i rSub { size 8{ ital "DP"} } =0} {}. The NMOS gate-to-source voltage is VDDVDD size 12{V rSub { size 8{ ital "DD"} } } {} and the NMOS is biased on the curve marked A in Figure 15a. The only point on the curve corresponding to iDN=0iDN=0 size 12{i rSub { size 8{ ital "DN"} } =0} {} occurs at vDSN=v0=0vDSN=v0=0 size 12{v rSub { size 8{ ital "DSN"} } =v rSub { size 8{0} } =0} {}. The output voltage is zero as long as the PMOS transistor is cut off, or vSGP=VDD−vI≤∣VThP∣vSGP=VDD−vI≤∣VThP∣ size 12{v rSub { size 8{ ital "SGP"} } =V rSub { size 8{ ital "DD"} } - v rSub { size 8{I} } <= lline V rSub { size 8{ ital "ThP"} } rline } {} . This means that the input voltage is in the range VDD−∣VThP∣≤vI≤VDDVDD−∣VThP∣≤vI≤VDD size 12{V rSub { size 8{ ital "DD"} } - lline V rSub { size 8{ ital "ThP"} } rline <= v rSub { size 8{I} } <= V rSub { size 8{ ital "DD"} } } {}.

Figure 16: CMOS inverter output voltage for input voltage in either high state or low state
Figure 16 (graphics16.png)

Figure 16 shows the voltage transfer characteristics generated thus far for the CMOS inverter. The more positive output voltage corresponds to a logic 1, or VOH=VDDVOH=VDD size 12{V rSub { size 8{ ital "OH"} } =V rSub { size 8{ ital "DD"} } } {}, and the more negative output voltage corresponds to a logic 0, or VOL=0VOL=0 size 12{V rSub { size 8{ ital "OL"} } =0} {}. When the output is in the logic 1 state, the NMOS transistor is cut off; when the output is in the logic 0 state, the PMOS transistor is cut off.

Ideally, the current in the CMOS inverter in either steady-state condition is zero, which means that, ideally, the quiescent power dissipation is zero. This result is attractive feature of CMOS digital circuits. In actuality, CMOS inverter circuits exhibit a small leakage current in both steady-state conditions due to the reverse-biased pn junctions. However, the power dissipation may be in the nanowatt range rather than in miliwatt range of NMOS inverters. Without this feature, VLSI would not be possible.

When the input voltage is just greater than VThNVThN size 12{V rSub { size 8{ ital "ThN"} } } {}, or

v I = v GSN − V ThN v I = v GSN − V ThN size 12{v rSub { size 8{I} } =v rSub { size 8{ ital "GSN"} } - V rSub { size 8{ ital "ThN"} } } {}

The NMOS begins to conduct and Q-point falls on the curve marked C in Figure 15a. The current is small and vDSN=VDDvDSN=VDD size 12{v rSub { size 8{ ital "DSN"} } =V rSub { size 8{ ital "DD"} } } {}, which means that the NMOS is biased in the saturation region. The PMOS source-to-drain voltage is small, so the PMOS is biased in the nonsaturation region. Setting iDN=iDPiDN=iDP size 12{i rSub { size 8{ ital "DN"} } =i rSub { size 8{ ital "DP"} } } {}, we can write

k N [ v GSN − V ThN ] 2 = k P [ 2 ( v GSP + V ThP ) V SDP − v SDP 2 ] k N [ v GSN − V ThN ] 2 = k P [ 2 ( v GSP + V ThP ) V SDP − v SDP 2 ] size 12{k rSub { size 8{N} } \[ v rSub { size 8{ ital "GSN"} } - V rSub { size 8{ ital "ThN"} } \] rSup { size 8{2} } =k rSub { size 8{P} } \[ 2 \( v rSub { size 8{ ital "GSP"} } +V rSub { size 8{ ital "ThP"} } \) V rSub { size 8{ ital "SDP"} } - v rSub { size 8{ ital "SDP"} } rSup { size 8{2} } \] } {} (41)

Relating the gate-to-source and drain-to-source voltages I each transistor to the inverter input and output voltages, respectively, we can rewrite Equation 41 as follows:

k N [ v I − V ThN ] 2 = k P [ 2 ( V DD − v I + V ThP ) ( V DD − v 0 ) − ( V DD − v 0 ) 2 ] k N [ v I − V ThN ] 2 = k P [ 2 ( V DD − v I + V ThP ) ( V DD − v 0 ) − ( V DD − v 0 ) 2 ] size 12{k rSub { size 8{N} } \[ v rSub { size 8{I} } - V rSub { size 8{ ital "ThN"} } \] rSup { size 8{2} } =k rSub { size 8{P} } \[ 2 \( V rSub { size 8{ ital "DD"} } - v rSub { size 8{I} } +V rSub { size 8{ ital "ThP"} } \) \( V rSub { size 8{ ital "DD"} } - v rSub { size 8{0} } \) - \( V rSub { size 8{ ital "DD"} } - v rSub { size 8{0} } \) rSup { size 8{2} } \] } {} (42)

Equation 42 relates the input and output voltage as long as the NMOS is biased in the saturation region and the PMOS is biased in the nonsaturation region.

The transition point for the PMOS is defined from

v SDP ( sat ) = v SGP + V ThP v SDP ( sat ) = v SGP + V ThP size 12{v rSub { size 8{ ital "SDP"} } \( ital "sat" \) =v rSub { size 8{ ital "SGP"} } +V rSub { size 8{ ital "ThP"} } } {} (43)

Using Equation 14, Equation 43 can be written

V DD − V 0 Pt = V DD − v IPt + V ThP V DD − V 0 Pt = V DD − v IPt + V ThP size 12{V rSub { size 8{ ital "DD"} } - V rSub { size 8{0 ital "Pt"} } =V rSub { size 8{ ital "DD"} } - v rSub { size 8{ ital "IPt"} } +V rSub { size 8{ ital "ThP"} } } {} (44)

or

V 0 Pt = v IPt − V ThP V 0 Pt = v IPt − V ThP size 12{V rSub { size 8{0 ital "Pt"} } =v rSub { size 8{ ital "IPt"} } - V rSub { size 8{ ital "ThP"} } } {} (45)

Where VOPtVOPt size 12{V rSub { size 8{ ital "OPt"} } } {} and VIPtVIPt size 12{V rSub { size 8{ ital "IPt"} } } {} are the PMOS output and input voltages, respectively, at the transition point.

The transition point for the NMOS is defined from

v SDN ( sat ) = v SGN − V ThN v SDN ( sat ) = v SGN − V ThN size 12{v rSub { size 8{ ital "SDN"} } \( ital "sat" \) =v rSub { size 8{ ital "SGN"} } - V rSub { size 8{ ital "ThN"} } } {} (46)

or

V 0 Nt = v INt − V ThN V 0 Nt = v INt − V ThN size 12{V rSub { size 8{0 ital "Nt"} } =v rSub { size 8{ ital "INt"} } - V rSub { size 8{ ital "ThN"} } } {} (47)

Where VONtVONt size 12{V rSub { size 8{ ital "ONt"} } } {} and VINtVINt size 12{V rSub { size 8{ ital "INt"} } } {} are the NMOS output and input voltages, respectively, at the transition point.

Keeping in mind that VThPVThP size 12{V rSub { size 8{ ital "ThP"} } } {} is negative for an enhancement-mode PMOS, Equation 45b and Equation 47b are plotted in Figure 17. We determine the input voltage at the transition points by setting the two drain currents equal to each other when both transistors are biased in the saturation region. The result is

k N ( v GSN − V ThN ) 2 = k P ( v SGP + V ThP ) 2 k N ( v GSN − V ThN ) 2 = k P ( v SGP + V ThP ) 2 size 12{k rSub { size 8{N} } \( v rSub { size 8{ ital "GSN"} } - V rSub { size 8{ ital "ThN"} } \) rSup { size 8{2} } =k rSub { size 8{P} } \( v rSub { size 8{ ital "SGP"} } +V rSub { size 8{ ital "ThP"} } \) rSup { size 8{2} } } {} (48)

Relating the gate-to-source voltages to the input voltage, Equation 48 becomes

k N ( v I − V ThN ) 2 = k P ( V DD − v I + V ThP ) 2 k N ( v I − V ThN ) 2 = k P ( V DD − v I + V ThP ) 2 size 12{k rSub { size 8{N} } \( v rSub { size 8{I} } - V rSub { size 8{ ital "ThN"} } \) rSup { size 8{2} } =k rSub { size 8{P} } \( V rSub { size 8{ ital "DD"} } - v rSub { size 8{I} } +V rSub { size 8{ ital "ThP"} } \) rSup { size 8{2} } } {} (49)

For this ideal case, the output voltage does not appear in Equation 49, and the input voltage is a constant, as long as the two transistors are biased in the saturation region.

Figure 17: Region of the CMOS transfer characteristics indicating NMOS and PMOS transistor bias conditions. The NMOS device is biased in the saturation region in areas A and B and in the nonsaturation region in area C. The PMOS device is biased in the saturation region in area B and C and in the nonsaturation region in area A
Figure 17 (graphics17.png)

Voltage vIvI size 12{v rSub { size 8{I} } } {} from Equation 49 is the input voltage at the PMOS and NMOS transition points. Solving for vIvI size 12{v rSub { size 8{I} } } {}, we find that

v I = V It = V DD + V ThP + k N k P V ThN 1 + k N k P v I = V It = V DD + V ThP + k N k P V ThN 1 + k N k P size 12{v rSub { size 8{I} } =V rSub { size 8{ ital "It"} } = { {V rSub { size 8{ ital "DD"} } +V rSub { size 8{ ital "ThP"} } + sqrt { { {k rSub { size 8{N} } } over {k rSub { size 8{P} } } } } V rSub { size 8{ ital "ThN"} } } over {1+ sqrt { { {k rSub { size 8{N} } } over {k rSub { size 8{P} } } } } } } } {} (50)

For vI>VItvI>VIt size 12{v rSub { size 8{I} } >V rSub { size 8{ ital "It"} } } {}, the NMOS is biased in the nonsaturation region and the PMOS is biased in the saturation region. Again equating the two drain currents, we have

k N 2 ( v GSN − V ThN ) v DSN − v DSN 2 = k P ( v SGP + V ThP ) 2 k N 2 ( v GSN − V ThN ) v DSN − v DSN 2 = k P ( v SGP + V ThP ) 2 size 12{k rSub { size 8{N} } left [2 \( v rSub { size 8{ ital "GSN"} } - V rSub { size 8{ ital "ThN"} } \) v rSub { size 8{ ital "DSN"} } - v rSub { size 8{ ital "DSN"} } rSup { size 8{2} } right ]=k rSub { size 8{P} } \( v rSub { size 8{ ital "SGP"} } +V rSub { size 8{ ital "ThP"} } \) rSup { size 8{2} } } {} (51)

Also, relating the gate-to-source and drain-to-source voltages to the input and output voltages, respectively, modifies Equation 51, as follows:

k N 2 ( v I − V ThN ) v 0 − v 0 2 = k P ( V DD − v I + V ThP ) 2 k N 2 ( v I − V ThN ) v 0 − v 0 2 = k P ( V DD − v I + V ThP ) 2 size 12{k rSub { size 8{N} } left [2 \( v rSub { size 8{I} } - V rSub { size 8{ ital "ThN"} } \) v rSub { size 8{0} } - v rSub { size 8{0} } rSup { size 8{2} } right ]=k rSub { size 8{P} } \( V rSub { size 8{ ital "DD"} } - v rSub { size 8{I} } +V rSub { size 8{ ital "ThP"} } \) rSup { size 8{2} } } {} (52)

Equation 52 relates the input and output voltages as long as the NMOS is biased in the nonsaturation region and the PMOS in the saturation region. Figure 18 shows the completed voltage transfer curve.

Figure 18: Complete voltage transfer characteristics, CMOS inverter
Figure 18 (graphics18.png)

CMOS Inverter Currents

When the CMOS inverter input voltage is either a logic 0 or a logic 1, the current in the circuit is zero since one of the transistor is off. When the input voltage is in the range VThN<vI<VDD−/VThP/VThN<vI<VDD−/VThP/ size 12{V rSub { size 8{ ital "ThN"} } <v rSub { size 8{I} } <V rSub { size 8{ ital "DD"} } - lline V rSub { size 8{ ital "ThP"} } rline } {}, both transistors conducting and a current exists in the inverter.

When the NMOS transistor is biased in the saturation region, the current in the inverter is controlled by vGSNvGSN size 12{v rSub { size 8{ ital "GSN"} } } {} and the PMOS source-to-drain voltage adjusts such that iDP=iDNiDP=iDN size 12{i rSub { size 8{ ital "DP"} } =i rSub { size 8{ ital "DN"} } } {}. This condition is demonstrated in Equation 52. We can write

i DN = i DP = k N ( v GSN − V ThN ) 2 = k N ( v I − V ThN ) 2 i DN = i DP = k N ( v GSN − V ThN ) 2 = k N ( v I − V ThN ) 2 size 12{i rSub { size 8{ ital "DN"} } =i rSub { size 8{ ital "DP"} } =k rSub { size 8{N} } \( v rSub { size 8{ ital "GSN"} } - V rSub { size 8{ ital "ThN"} } \) rSup { size 8{2} } =k rSub { size 8{N} } \( v rSub { size 8{I} } - V rSub { size 8{ ital "ThN"} } \) rSup { size 8{2} } } {} (53)

Taking the square root yields

i DN = i DP = k N ( v I − V ThN ) i DN = i DP = k N ( v I − V ThN ) size 12{ sqrt {i rSub { size 8{ ital "DN"} } } = sqrt {i rSub { size 8{ ital "DP"} } } = sqrt {k rSub { size 8{N} } } \( v rSub { size 8{I} } - V rSub { size 8{ ital "ThN"} } \) } {} (54)

As long as the NMOS transistor is biased in the saturation region, the square root of the CMOS inverter is a linear function of the input voltage.

When the PMOS transistor is biased in the saturation region, the current in the inverter is controlled by vSGPvSGP size 12{v rSub { size 8{ ital "SGP"} } } {} and the NMOS drain-to-source voltage adjusts such that iDP=iDNiDP=iDN size 12{i rSub { size 8{ ital "DP"} } =i rSub { size 8{ ital "DN"} } } {}. This condition is demonstrated in Equation 51. Using Equation 52, we can write that

i DN = i DP = k P ( V DD − v I + V ThP ) 2 i DN = i DP = k P ( V DD − v I + V ThP ) 2 size 12{i rSub { size 8{ ital "DN"} } =i rSub { size 8{ ital "DP"} } =k rSub { size 8{P} } \( V rSub { size 8{ ital "DD"} } - v rSub { size 8{I} } +V rSub { size 8{ ital "ThP"} } \) rSup { size 8{2} } } {} (55)

Taking the square root yields

i DN = i DP = k N ( V DD − v I + V ThP ) i DN = i DP = k N ( V DD − v I + V ThP ) size 12{ sqrt {i rSub { size 8{ ital "DN"} } } = sqrt {i rSub { size 8{ ital "DP"} } } = sqrt {k rSub { size 8{N} } } \( V rSub { size 8{ ital "DD"} } - v rSub { size 8{I} } +V rSub { size 8{ ital "ThP"} } \) } {} (56)

As long as the PMOS transistor is biased in the saturation region, the square root of the CMOS inverter current is also a linear function of the input voltage.

(Reference) shows plots of the square root of the inverter current for two values of VDDVDD size 12{V rSub { size 8{ ital "DD"} } } {} bias. These curves are quasi-static characteristics in that no current is diverted into a capacitive load. At the inverter switching point, both transistors are biased in the saturation region and both transistors influence the current. At the switching point, actual current characteristic does not have a sharp discontinuity in the slope. The channel length modulation parameter λλ size 12{λ} {} also influences the current characteristics at the peak values. However, the curves in Figure 19 are excellent approximations.

Figure 19: Square root of inverter current versus input voltage, CMOS inverter biased at either VDD = 5 V or VDD = 10 V
Figure 19 (graphics19.png)

Power Dissipation

In the quiescent or static state, in which the input is either a logic 0 or logic 1; power dissipation in the CMOS inverter is virtually zero. However, during the switching cycle from one to another, current flows and power is dissipated. The CMOS inverter and logic circuits are used to drive other MOS devices for which the input impedance is a capacitance. During the switching cycle, then, this load capacitance must be charged and discharged.

In Figure 20, the output switches from its low to its high state. The input is switched low, the PMOS gate is at zero volts, and the NMOS is cut off. The load capacitance CL must be charged through the PMOS device. Power dissipation in the PMOS transistor is given by

P P = i L v SD = i L ( V DD − v 0 ) P P = i L v SD = i L ( V DD − v 0 )