INTRODUCTION

Having learned the basic laws and theorems for circuit analysis, we are now ready to study an active circuit element of paramount importance: the operational amplifier or op amp for short. The op amp is a versatile circuit building block.

The op amp is an electronic unit that behaves like a voltage-controlled voltage source.

It can also be used in making a voltage or current controlled current source. An op amp can sum signal, amplify signal, integrate it, or differentiate it. The ability of the op amp to perform these mathematical operations is the reason it is called an operational amplifier. It is also the reason for the widespread use of op amps in analog design. Op amps are popular in practical circuit designs because they are versatile, inexpensive, ease to use, and fun to work with.

We begin by discussing the ideal op amp and later consider the nonideal op amp. Using nodal analysis as a tool, we consider ideal op amp circuits such as the inverter, voltage follower, summer, and difference amplifier. Finally, we learn an op amp is used in digital-to-analog converters and instrumentation amplifiers.

OPERATIONAL AMPLIFIERS

An operational amplifier is designed so that it performs some mathematical operations when external components, such as resistors and capacitors, are connected to its terminals. Thus,

An op amp is an active circuit element designed to perform mathematical operations of addition, substraction, multiplication, division, differentiation, and integration.

The op amp is an electronic device consisting of a complex arrangement of resistors, transistors, capacitors, and diodes. A full discussion of what is inside the op amp is beyond the scope of this block. It will suffice to treat the op amp as a circuit building block and simply study what takes place at its terminals.

Op amps are commercially available in integrated circuit packages in several forms. Figure 1 shows a typical op amp package. A typical one is the eight-pin dual in-line package (or DIP), shown in Figure 2(a). Pin or terminal 8 is unused, and terminals 1 and 5 are of little concern to us. The five important terminals are:

1. The inverting input, pin 2,

2. The noninverting input, pin 3,

3. The output, pin 6,

4. The positive power supply V+V+ size 12{V rSup { size 8{+{}} } } {}, pin 7,

5. The negative power supply V−V− size 12{V rSup { size 8{ - {}} } } {}, pin 4.

Figure 1: A typical operational amplifier.

The circuit symbol for the op amp is the triangle in Figure 2(b); as shown, the op amp has two inputs and one output. The inputs are marked with minus (-) and plus (+) to specify inverting and noninverting inputs, respectively. An input applied to the to the noninverting terminal will appear with the same polarity at the output, while an input applied to the inverting terminal will appear inverted at the output.

Figure 2: A typical op amp: a) pin configuration, b) circuit symbol.

As an active element, the op amp must be powered by a voltage supply as typically show in Figure 3. Although the power supplies are often ignored in op amp circuit diagrams for the sake of simplicity, the power supply currents must not be overlooked. By KCL,

The equivalent circuit model of an op amp is shown in Figure 4. The output section consists of a voltage-controlled source in series with the output resistance R0. It is evident from Figure 4 that the input resistance g, is the Thevenin equivalent resistance seen at the input terminals, while the output resistance R0R0 size 12{R rSub { size 8{0} } } {} is the Thevenin equivalent resistance seen at the output. The differential input voltage vdvd size 12{v rSub { size 8{d} } } {} is given by

Where v1v1 size 12{v rSub { size 8{1} } } {} is the voltage between the inverting terminal and ground and v2v2 size 12{v rSub { size 8{2} } } {} is the voltage between the noninverting terminal and ground. The op amp senses the difference between the two inputs, multiplies it by the gain A, and cause the resulting voltage to appear at the output. Thus, the output v0v0 size 12{v rSub { size 8{0} } } {} is given by

A is called the open-loop voltage gain because it is the gain of the op amp without any external feedback from output to input. Table 1 shows typical values of voltage gain A, input resistance RiRi size 12{R rSub { size 8{i} } } {}, output resistance R0R0 size 12{R rSub { size 8{0} } } {}, and supply voltage VCCVCC size 12{V rSub { size 8{ ital "CC"} } } {}.

Figure 3: Powering the op amp.

Typical ranges for op amp parameters.

The concept of feedback is crucial to our understanding of op amp circuits. A negative feedback is achieved when the output is fed back to the inverting terminal of the op amp. When there is a feedback path from output to input of the op amp, the ratio of the output voltage to the input voltage is called the closed loop gain. As a result of the negative feedback, it can be shown that the closed-loop gain is almost insensitive to the open-loop gain A of the op amp. For this reason, op amps are used in circuit with feedback paths.

Figure 4: The equivalent circuit of the nonideal opamp.

A practical limitation of the op amp is that the magnitude of its output voltage cannot exceed ∣VCC∣∣VCC∣ size 12{ lline V rSub { size 8{ ital "CC"} } rline } {}. In other words, the output voltage is dependent on and is limited by the power supply voltage. Figure 5 illustrates that the op amp can operate in three modes, depending on the differential input voltage vdvd size 12{v rSub { size 8{d} } } {}:

1. Positive saturation, v0=VCCv0=VCC size 12{v rSub { size 8{0} } =V rSub { size 8{ ital "CC"} } } {},

2. Linear region, −VCC≤v0=Avd≤VCC−VCC≤v0=Avd≤VCC size 12{ - V rSub { size 8{ ital "CC"} } <= v rSub { size 8{0} } = ital "Av" rSub { size 8{d} } <= V rSub { size 8{ ital "CC"} } } {},

3. Negative saturation, v0=−VCCv0=−VCC size 12{v rSub { size 8{0} } = - V rSub { size 8{ ital "CC"} } } {}.

Figure 5: Op amp output voltage Vo as a function of the different input voltage Vd.

Although we shall always operate the op amp in the linear region, the possibility of saturation must be borne in mind when one design with op amps, to avoid designing op amp circuits that will not work in the laboratory.

IDEAL OPERATIONAL AMPLIFIERS

To facilitate the understanding of op amp circuits, we will assume ideal op amp. An op amp is ideal if it has the following characteristics:

An ideal op amp is an amplifier with infinite open-loop gain, infinite input resistance and zero output resistance.

Although assuming an ideal op amp provides only approximate analysis, most modern amplifiers have such large gain and input impedance that the approximate analysis is a good one. Unless stated otherwise, we will assume from now on that every op amp is ideal.

Figure 6: Ideal op amp model.

For circuit analysis, the ideal op amp is illustrated in Figure 6, which is derived from the nonideal model in Figure 4. Two important characteristics of the op amp are:

1. The current into both input terminals are zero:

and

i2=0i2=0 size 12{i rSub { size 8{2} } =0} {}

This is due to infinite input resistance. An infinite resistance between the input terminals implies that an open circuit exists there and current cannot enter the op amp. But the output circuit is not necessary zero according to Equation 1.

2. The voltage across the input terminals is negligibly small; i.e.,

Or

Thus, an ideal op amp has zero current into its two input terminals and negligibly small voltage between the two input terminals. Equation 4 and Equation 6 are extremely important and should be regarded as the key handles to analyzing op amp circuits.

INVERTING AMPLIFIER

In this and following sections, we consider some useful op amp circuits that often serve as modules for designing more complex circuits. The first of such op amp circuits is the inverting amplifier shown in Equation 9. In this circuit, the noninverting circuit is grounded. vi is connected to the inverting input through RiRi size 12{R rSub { size 8{i} } } {}, and the feedback resistor RfRf size 12{R rSub { size 8{f} } } {} is connected between the inverting input and output. Our goal is to obtain the relationship the input voltage vi and the output voltage v0. Applying KCL at node 1,

But v1=v2=0v1=v2=0 size 12{v rSub { size 8{1} } =v rSub { size 8{2} } =0} {} for an ideal op amp, since the noninverting terminal is grounded. Hence,

v i R i = − v 0 R f v i R i = − v 0 R f size 12{ { {v rSub { size 8{i} } } over {R rSub { size 8{i} } } } = { { - v rSub { size 8{0} } } over {R rSub { size 8{f} } } } } {}

Or

The voltage gain is Av=v0/vi=−Rf/RiAv=v0/vi=−Rf/Ri size 12{A rSub { size 8{v} } = {v rSub { size 8{0} } } slash {v rSub { size 8{i} } = - {R rSub { size 8{f} } } slash {R rSub { size 8{i} } } } } {}. The designation of the circuit in Figure 7 as an inverter arises from the negative sign. Thus,

An inverting amplifier reverses the polarity of the input signal while amplifying it.

Note that the gain is the feedback resistance divided by the input resistance which means that the gain depends only on the external elements connected to the op amp. In view of Equation 8, an equivalent circuit for the inverting amplifier is shown in Figure 8. The inverting amplifier is used, for example, in current to voltage converter.

Figure 7: The inverting amplifier.

Figure 8: An equivalent circuit for the inverter in Figure 7.

NONINVERTING AMPLIFIER

Another important application of the op amp is the noninverting amplifier shown in Figure 9. In this case, the input voltage vivi size 12{v rSub { size 8{i} } } {} is applied directly at the noninverting input terminal and resistor RiRi size 12{R rSub { size 8{i} } } {} is connected between ground and the inverting terminal. We are interested in the output voltage and the voltage gain. Application of KCL at the inverting terminal gives

But v1=v2=viv1=v2=vi size 12{v rSub { size 8{1} } =v rSub { size 8{2} } =v rSub { size 8{i} } } {}. Equation 9 becomes

− v i R 1 = v i − v 0 R f − v i R 1 = v i − v 0 R f size 12{ { { - v rSub { size 8{i} } } over {R rSub { size 8{1} } } } = { {v rSub { size 8{i} } - v rSub { size 8{0} } } over {R rSub { size 8{f} } } } } {}

Or

The voltage gain is Av=v0/vi=1+Rf/R1Av=v0/vi=1+Rf/R1 size 12{A rSub { size 8{v} } = {v rSub { size 8{0} } } slash {v rSub { size 8{i} } =1+ {R rSub { size 8{f} } } slash {R rSub { size 8{1} } } } } {}, which does not have a negative sign. Thus, the output has the same polarity as the input.

A noninverting amplifier is an op amp circuit designed to provide a positive voltage gain.

Again we notice that the gain depends only on the external resistors.

Figure 9: The noninverting amplifier.

Notice that if feedback resistor Rf=0Rf=0 size 12{R rSub { size 8{f} } =0} {} (short circuit) or R1=∞R1=∞ size 12{R rSub { size 8{1} } = infinity } {} (open circuit) or both, the gain becomes 1. Under these conditions ( Rf=0Rf=0 size 12{R rSub { size 8{f} } =0} {} and R1=∞R1=∞ size 12{R rSub { size 8{1} } = infinity } {} ), the circuit in Figure 9 becomes that shown in Figure 10, which is called a voltage follower (or unity gain amplifier) because the output follows the input. Thus, for a voltage follower

Figure 10: The voltage follower.

Such circuit has very high input impedance and is therefore useful as an intermediate-stage (or buffer) amplifier to isolate one circuit from another as portrayed in Figure 11. The voltage follower minimizes interaction between the two stages and eliminates interstage loading.

Figure 11: A voltage follower used to isolate two cascaded stages of a circuit.

SUMMING AMPLIFIER

Besides amplification, the op amp can perform addition and subtraction. The addition is performed by the summing amplifier covered in this section; the subtraction is performed by the difference amplifier covered in the next section.

A summing amplifier is an op amp circuit that several inputs and produce an output that is the weighted sum of the inputs.

The summing amplifier, shown in Figure 12, is variation of the inverting amplifier. It takes advantage of the fact that the inverting configuration can handle many inputs at the same time. We keep in mind that the current entering each op amp input is zero. Applying KCL at node a gives

But

i 1 = v 1 − v a R 1 , i 2 = v 2 − v a R 2 i 1 = v 1 − v a R 1 , i 2 = v 2 − v a R 2 size 12{i rSub { size 8{1} } = { {v rSub { size 8{1} } - v rSub { size 8{a} } } over {R rSub { size 8{1} } } } ,i rSub { size 8{2} } = { {v rSub { size 8{2} } - v rSub { size 8{a} } } over {R rSub { size 8{2} } } } } {}

We note that va=0va=0 size 12{v rSub { size 8{a} } =0} {} and substitute Equation 13 into Equation 12. We get

Indicating that the output voltage is a weighted sum of the inputs. For this reason, the circuit in Figure 18 is called a summer. Needless to say, the summer can have more than three inputs.

Figure 12: The summing amplifier.

DIFFERENCE AMPLIFIER

Difference (or differential) amplifiers are used in various applications where there is need to amplify the difference between two input signals. They are first cousins of the instrumentation amplifier, the most useful and popular amplifier, which we will discuss in section 9.

A difference amplifier is a device that amplifies the difference between two inputs but rejects any signals common to the two inputs.

Consider the op amp circuit shown in Figure 13. Keep in mind that zero currents enter the op amp terminals. Applying KCL to node a,

v 1 − v a R 1 = v a − v 0 R 2 v 1 − v a R 1 = v a − v 0 R 2 size 12{ { {v rSub { size 8{1} } - v rSub { size 8{a} } } over {R rSub { size 8{1} } } } = { {v rSub { size 8{a} } - v rSub { size 8{0} } } over {R rSub { size 8{2} } } } } {}

or

Figure 13: Difference amplifier.

Applying KCL to node b,

v 2 − v b R 3 = v b − 0 R 4 v 2 − v b R 3 = v b − 0 R 4 size 12{ { {v rSub { size 8{2} } - v rSub { size 8{b} } } over {R rSub { size 8{3} } } } = { {v rSub { size 8{b} } - 0} over {R rSub { size 8{4} } } } } {}

Or

but va=vbva=vb size 12{v rSub { size 8{a} } =v rSub { size 8{b} } } {}. Substituting Figure 14 into Figure 13 yields

Or

v 0 = R 2 R 1 ( 1 + R 1 / R 2 ) ( 1 + R 3 / R 4 ) v 2 − R 2 R 1 v 1 v 0 = R 2 R 1 ( 1 + R 1 / R 2 ) ( 1 + R 3 / R 4 ) v 2 − R 2 R 1 v 1 size 12{v rSub { size 8{0} } = { {R rSub { size 8{2} } } over {R rSub { size 8{1} } } } { { \( 1+R rSub { size 8{1} } /R rSub { size 8{2} } \) } over { \( 1+R rSub { size 8{3} } /R rSub { size 8{4} } \) } } v rSub { size 8{2} } - { {R rSub { size 8{2} } } over {R rSub { size 8{1} } } } v rSub { size 8{1} } } {}

Since a difference amplifier must reject a signal common to the two inputs, the amplifier must have the property that v0=0v0=0 size 12{v rSub { size 8{0} } =0} {} when v1=v2v1=v2 size 12{v rSub { size 8{1} } =v rSub { size 8{2} } } {}. This property exists when

Thus, when the op amp circuit is a difference amplifier, Figure 15 becomes

Which indicated that this amplifier has a differential gain of AdR2/R1AdR2/R1 size 12{A rSub { size 8{d} } {R rSub { size 8{2} } } slash {R rSub { size 8{1} } } } {}. This factor is a closed-loop differential gain.

If R2=R1R2=R1 size 12{R rSub { size 8{2} } =R rSub { size 8{1} } } {} and R3=R4R3=R4 size 12{R rSub { size 8{3} } =R rSub { size 8{4} } } {}, the difference amplifier becomes a substractor, with the output

As previously stated, another important characteristic of electronic circuits is the input resistance. The differential input resistance of the differential amplifier can be determined using the circuit shown in Figure 14. In the Figure, we have imposed the condition given in Equation 18 and have set R1=R3R1=R3 size 12{R rSub { size 8{1} } =R rSub { size 8{3} } } {} and R2=R4R2=R4 size 12{R rSub { size 8{2} } =R rSub { size 8{4} } } {}. The input resistance is then defined as

Taking into account the virtual short concept, we can write a loop equation, as follows:

Therefore, the input resistance is

Figure 14: Circuit for measuring differential input resistance of op amp difference amplifier.

In the ideal difference amplifier, the output v0 is zero when v1=v2v1=v2 size 12{v rSub { size 8{1} } =v rSub { size 8{2} } } {}. However, an inspection of Equation 17 shows that this condition is not satisfied if R4/R3≠R2/R1R4/R3≠R2/R1 size 12{ {R rSub { size 8{4} } } slash {R rSub { size 8{3} } <> {R rSub { size 8{2} } } slash {R rSub { size 8{1} } } } } {}. When v1=v2v1=v2 size 12{v rSub { size 8{1} } =v rSub { size 8{2} } } {}, the input is called a common mode input signal. The common mode input voltage is defined as

The common mode gain is then defined as

Ideally, when a common mode signal is applied, v0=0v0=0 size 12{v rSub { size 8{0} } =0} {} and Acm=0Acm=0 size 12{A rSub { size 8{ ital "cm"} } =0} {}.

A nonzero common mode gain may be generated in actual op-amp circuits. A figure of merit for a difference amplifier is the common mode rejection ratio (CMRR), which is defined as the amplitude of the ratio of differential gain to common mode gain, or

Usually, the CMRR is expressed in decibels, as follows:

Ideally, the common mode rejection ratio is infinite. In an actual differential amplifier, we would like the common mode rejection ratio to be as large as possible.

CASCADED OP AMP CIRCUITS

As we know, op amp circuits are modules or building blocks for designing complex circuits. It is necessary in practical applications to connect op amp circuits in cascade (i.e. head to tail) to achieve a large overall gain. In general, two circuits are cascaded when they are connected in tandem, one behind another in a single file.

A cascade connection is a head to tail arrangement of two or more op amp circuits such that the output of one is the input of the next.

When op amp circuits are cascaded, each circuit in the string is called a stage; one original input signal is increased by the gain of the individual stage. Op amp circuits have the advantage that they can be cascaded without changing their input-output relationships. This is due to the fact that each (ideal) op amp circuit has infinite input resistance and zero output resistance. Figure 15 displays a block diagram representation of three op amp circuits in cascade. Since the output of one stage is the input to the next stage, the overall gain of the cascade connection is the product of the gain of the individual op amp circuits, or

Although the cascade connection does not effect the op amp input-output relationships, care must be exercised in the design of an actual op amp circuit to ensure that the load due to the next stage in the cascade does not saturate the op amp.

Figure 15: A three stage cascaded connection.

APPLICATIONS

The op amp is a fundamental building block in modern electronic instrumentation. It is used extensively in many devices, along with resistors and other passive elements. Its numerous practical applications include instrumentation amplifiers, digital to analog converters, analog computers, level shifters, filters, calibration circuits, inverters, summers, integrators, differentiators, substractors, logarithmic amplifiers, comparators, oscillators, rectifiers, regulators, voltage to current converters, current to voltage converters and clippers. Some of these we have already considered. We will consider four more applications here: the digital-to-analog converter, the instrumentation amplifier the log amplifier and anti-log amplifier.

Digital-to-Analog Converter

The digital-to-analog converter (DAC) transforms digital signal into analog form. A typical example of a four-bit DAC is illustrated in Figure 16(a). The four-bit DAC can be realized in many ways. A simple realization is the binary weighted ladder, shown in Figure 16(b). The bits are weights according to the magnitude of their place value, by descending value of Rf/RnRf/Rn size 12{ {R rSub { size 8{f} } } slash {R rSub { size 8{n} } } } {} so that each lesser bit has half the weight of the next higher. This is obviously an inverting summing amplifier. The output is related to the inputs as shown in Equation 14. Thus,

− V 0 = R f R 1 V 1 + R f R 2 V 2 + R f R 3 V 3 + R f R 4 V 4 − V 0 = R f R 1 V 1 + R f R 2 V 2 + R f R 3 V 3 + R f R 4 V 4 size 12{ - V rSub { size 8{0} } = { {R rSub { size 8{f} } } over {R rSub { size 8{1} } } } V rSub { size 8{1} } + { {R rSub { size 8{f} } } over {R rSub { size 8{2} } } } V rSub { size 8{2} } + { {R rSub { size 8{f} } } over {R rSub { size 8{3} } } } V rSub { size 8{3} } + { {R rSub { size 8{f} } } over {R rSub { size 8{4} } } } V rSub { size 8{4} } } {} (29)

Input V1V1 size 12{V rSub { size 8{1} } } {} is called the most significant bit (MSB), while input V4V4 size 12{V rSub { size 8{4} } } {} is the least significant bit (LSB). Each of the four binary inputs V1V1 size 12{V rSub { size 8{1} } } {}, …, V4V4 size 12{V rSub { size 8{4} } } {} can assume only two voltage levels, 0 or 1 V. By using the proper input and feedback resistor values, the DAC provides a single output that is proportional to the inputs.

Figure 16: Four bits DAC: a) block diagram, b) binary weighted ladder type.

Instrumentation Amplifiers

One of the most useful and versatile op amp circuits for precision measurement and process control is the instrumentation amplifier (IA), so called because of its widespread use in measurement systems. Typical applications of IA include isolation amplifiers, thermocouple amplifiers, and data acquisition systems.

The instrumentation amplifier is an extension of the difference amplifier in that it amplifies the difference between its input signals. An instrumentation amplifier is shown in Figure 17. An instrumentation amplifier typically consists of three op amps and seven resistors.

We recognize that the amplifier A2A2 size 12{A rSub { size 8{2} } } {} in Figure 17. is a difference amplifier. Thus, from Equation 19. ,

v 0 = R 2 R 1 ( v 02 − v 01 ) v 0 = R 2 R 1 ( v 02 − v 01 ) size 12{v rSub { size 8{0} } = { {R rSub { size 8{2} } } over {R rSub { size 8{1} } } } \( v rSub { size 8{"02"} } - v rSub { size 8{"01"} } \) } {} (30)

Since the op amps A1A1 size 12{A rSub { size 8{1} } } {} and A2A2 size 12{A rSub { size 8{2} } } {} draw no current, current i flows through the three resistors as though they were in series. Hence,

v 01 − v 02 = i ( R 3 + R 4 + R 3 ) = i ( 2R 3 + R 4 ) v 01 − v 02 = i ( R 3 + R 4 + R 3 ) = i ( 2R 3 + R 4 ) size 12{v rSub { size 8{"01"} } - v rSub { size 8{"02"} } =i \( R rSub { size 8{3} } +R rSub { size 8{4} } +R rSub { size 8{3} } \) =i \( 2R rSub { size 8{3} } +R rSub { size 8{4} } \) } {} (31)

But

i = v a − v b R 4 i = v a − v b R 4 size 12{i= { {v rSub { size 8{a} } - v rSub { size 8{b} } } over {R rSub { size 8{4} } } } } {}

Figure 17: Instrumentation amplifier.

And va=v1va=v1 size 12{v rSub { size 8{a} } =v rSub { size 8{1} } } {}, vb=v2vb=v2 size 12{v rSub { size 8{b} } =v rSub { size 8{2} } } {}. Therefore,

i = v 1 − v 2 R 4 i = v 1 − v 2 R 4 size 12{i= { {v rSub { size 8{1} } - v rSub { size 8{2} } } over {R rSub { size 8{4} } } } } {} (32)

Inserting Equation 31. and Equation 32 into Equation 30 gives

v 0 = R 2 R 1 ( 1 + 2R 3 R 4 ) ( v 2 − v 1 ) v 0 = R 2 R 1 ( 1 + 2R 3 R 4 ) ( v 2 − v 1 ) size 12{v rSub { size 8{0} } = { {R rSub { size 8{2} } } over {R rSub { size 8{1} } } } \( 1+ { {2R rSub { size 8{3} } } over {R rSub { size 8{4} } } } \) \( v rSub { size 8{2} } - v rSub { size 8{1} } \) } {} (33)

For convenience, the amplifier is shown again in Figure 18(a), where the resistors are made equal except for the external gain-setting resistor R4=RGR4=RG size 12{R rSub { size 8{4} } =R rSub { size 8{G} } } {}, connected between the gain set terminals. Figure 18(b) shows its schematic symbol. From Equation 33 we have

v 0 = A v ( v 2 − v 1 ) v 0 = A v ( v 2 − v 1 ) size 12{v rSub { size 8{0} } =A rSub { size 8{v} } \( v rSub { size 8{2} } - v rSub { size 8{1} } \) } {} (34)

Where the voltage gain is

A v = 1 + 2R R G A v = 1 + 2R R G size 12{A rSub { size 8{v} } =1+ { {2R} over {R rSub { size 8{G} } } } } {}

Figure 18: a) The instrumentation amplifier with an external resistance to adjust the gain, b) schematic diagram.

As shown in Figure 19, the instrumentation amplifier amplifies small differential signal voltages superimposed on larger common-mode voltages. Since the common-mode voltages are equal, they cancel each other.

The IA has three major characteristics:

1. The voltage gain is adjusted by one external resistor RGRG size 12{R rSub { size 8{G} } } {}.
2. The input impedance of both inputs is very high and does not vary as the gain is adjusted.
3. The output v0v0 size 12{v rSub { size 8{0} } } {} depends on the difference between the inputs v1v1 size 12{v rSub { size 8{1} } } {} and v2v2 size 12{v rSub { size 8{2} } } {}, not on the voltage common to them (common mode voltage).

Due to the widespread use of IAs, manufacturers have developed these amplifiers on single package units. A typical example is the LH0036, developed by National Semiconductor. The gain can be varied from 1 to 1,000 by an external resistor whose value may vary from 100 ΩΩ size 12{ %OMEGA } {} to 10 k ΩΩ size 12{ %OMEGA } {}.

Figure 19: The IA rejects common voltages but amplifiers small signal voltages.

Log Amplifier

In this chapter, we have used linear passive elements in conjunction with the op-amp. If a nonlinear device, such as a diode, is used with an op-amp, a nonlinear transfer function is produced.

Consider the circuit in Figure 20. The diode is to be forward biased, so the input signal voltage is limited to positive values. The diode current is

i D = I S e V D V T − 1 i D = I S e V D V T − 1 size 12{i rSub { size 8{D} } =I rSub { size 8{S} } left [e rSup { size 8{ { {V rSub { size 6{D} } } over {V rSub { size 6{T} } } } } } - 1 right ]} {} (35)

If the diode is sufficiently forward biased, the (-1) term is negligible, and

i D = I S e v D V T i D = I S e v D V T size 12{i rSub { size 8{D} } =I rSub { size 8{S} } e rSup { size 8{ { {v rSub { size 6{D} } } over {V rSub { size 6{T} } } } } } } {} (36)

Figure 20: Simple log amplifier.

The input current can be written

i 1 = v i R 1 i 1 = v i R 1 size 12{i rSub { size 8{1} } = { {v rSub { size 8{i} } } over {R rSub { size 8{1} } } } } {} (37)

And the output voltage is given by

v 0 = − v D v 0 = − v D size 12{v rSub { size 8{0} } = - v rSub { size 8{D} } } {} (38)

Noting that i1=iDi1=iD size 12{i rSub { size 8{1} } =i rSub { size 8{D} } } {}, we can write

i 1 = v i R 1 = i D = I s e − v 0 V T i 1 = v i R 1 = i D = I s e − v 0 V T size 12{i rSub { size 8{1} } = { {v rSub { size 8{i} } } over {R rSub { size 8{1} } } } =i rSub { size 8{D} } =I rSub { size 8{s} } e rSup { size 8{ { { - v rSub { size 6{0} } } over {V rSub { size 6{T} } } } } } } {} (39)

If we take the natural log of both sides of this equation, we obtain

ln v i I S R 1 = − v 0 V T ln v i I S R 1 = − v 0 V T size 12{"ln" { {v rSub { size 8{i} } } over {I rSub { size 8{S} } R rSub { size 8{1} } } } = - { {v rSub { size 8{0} } } over {V rSub { size 8{T} } } } } {} (40)

v 0 = − V T ln ( v i I S R 1 ) v 0 = − V T ln ( v i I S R 1 ) size 12{v rSub { size 8{0} } = - V rSub { size 8{T} } "ln" \( { {v rSub { size 8{i} } } over {I"" lSub { size 8{S} } R rSub { size 8{1} } } } \) } {} (41)

Equation 41 indicates that, for this circuit, the output voltage is proportional to the log of the input voltage. One disadvantage of this circuit is that the reverse-saturation current ISIS size 12{I rSub { size 8{S} } } {} is a strong function of temperature, and it varies substantially from one diode to another.

The reverse-saturation current in Equation 41 is eliminated in the circuit shown in Figure 21, which uses two bipolar transistors instead of a single diode. However, the circuit is considerably more complicated than the diode current in Figure 20.

Figure 21: Op amp log amplifier.

Before we begin the analysis, we must first consider the two transistors, Q1Q1 size 12{Q rSub { size 8{1} } } {} and Q2Q2 size 12{Q rSub { size 8{2} } } {}. In order for the circuit to operate properly, the transistors must be biased in the active region. The collector current iC1iC1 size 12{i rSub { size 8{C1} } } {} must therefore be positive, which implies that i1i1 size 12{i rSub { size 8{1} } } {} and vivi size 12{v rSub { size 8{i} } } {} must be positive. In turn, a positive input voltage vivi size 12{v rSub { size 8{i} } } {} means that the voltage vxvx size 12{v rSub { size 8{x} } } {} at the inverting terminal is slightly positive, which produces a negative output voltage at v,v, size 12{v rSup { size 8{,} } } {}. A negative v,v, size 12{v rSup { size 8{,} } } {} forward biases both B-E junctions, and both Q1Q1 size 12{Q rSub { size 8{1} } } {} and Q2Q2 size 12{Q rSub { size 8{2} } } {} are biased in the active region.

With Q1Q1 size 12{Q rSub { size 8{1} } } {} and Q2Q2 size 12{Q rSub { size 8{2} } } {} biased “on”, assuming Q1Q1 size 12{Q rSub { size 8{1} } } {} and Q2Q2 size 12{Q rSub { size 8{2} } } {} are matched and at the same temperature, the collector currents are

i C1 = I S e V BE 1 V T i C1 = I S e V BE 1 V T size 12{i rSub { size 8{C1} } =I rSub { size 8{S} } e rSup { size 8{ { {V rSub { size 6{ ital "BE"1} } } over {V rSub { size 6{T} } } } } } } {} (42)

And

i C2 = I S e V BC 2 V T i C2 = I S e V BC 2 V T size 12{i rSub { size 8{C2} } =I rSub { size 8{S} } e rSup { size 8{ { {V rSub { size 6{ ital "BC"2} } } over {V rSub { size 6{T} } } } } } } {} (43)

where ISIS size 12{I rSub { size 8{S} } } {} is reverse-saturation current in each transistor. If we take the natural log of both equations, we have

ln i C1 = ln I S + v BE 1 V T ln i C1 = ln I S + v BE 1 V T size 12{"ln"i rSub { size 8{C1} } ="ln"I rSub { size 8{S} } + { {v rSub { size 8{ ital "BE"1} } } over {V rSub { size 8{T} } } } } {} (44)

And

ln i C1 = ln I S + v BE 1 V T ln i C1 = ln I S + v BE 1 V T size 12{"ln"i rSub { size 8{C1} } ="ln"I rSub { size 8{S} } + { {v rSub { size 8{ ital "BE"1} } } over {V rSub { size 8{T} } } } } {} (45)

The B-E voltage of each transistor is then

v BE 1 = V T ln i C1 − ln I S v BE 1 = V T ln i C1 − ln I S size 12{v rSub { size 8{ ital "BE"1} } =V rSub { size 8{T} } left ["ln"i rSub { size 8{C1} } - "ln"I rSub { size 8{S} } right ]} {} (46)

And

v BE 2 = V T ln i C2 − ln I S v BE 2 = V T ln i C2 − ln I S size 12{v rSub { size 8{ ital "BE"2} } =V rSub { size 8{T} } left ["ln"i rSub { size 8{C2} } - "ln"I rSub { size 8{S} } right ]} {} (47)

For the noninverting terminal of op-amp A2A2 size 12{A rSub { size 8{2} } } {}, the input voltage with respect to ground is found by writing a KVL equation through the B-E junctions of Q1Q1 size 12{Q rSub { size 8{1} } } {} and Q2Q2 size 12{Q rSub { size 8{2} } } {}, as follows:

v 0i = v BE 2 − v BE 1 v 0i = v BE 2 − v BE 1 size 12{v rSub { size 8{0i} } =v rSub { size 8{ ital "BE"2} } - v rSub { size 8{ ital "BE"1} } } {} (48)

Substituting Equation 46 and Equation 47 into Equation 48, we obtain

v 01 = V T [ ( ni C2 − ln I S ) − ( ln i C1 − ln I S ) v 01 = V T [ ( ni C2 − ln I S ) − ( ln i C1 − ln I S ) size 12{v rSub { size 8{"01"} } =V rSub { size 8{T} } \[ \( ital "ni" rSub { size 8{C2} } - "ln"I rSub { size 8{S} } \) - \( "ln"i rSub { size 8{C1} } - "ln"I rSub { size 8{S} } \) } {} (49)

Or

v 01 = V T ln i C2 − ln i C1 = − V T ln ( i C1 i C2 ) v 01 = V T ln i C2 − ln i C1 = − V T ln ( i C1 i C2 ) size 12{v rSub { size 8{"01"} } =V rSub { size 8{T} } left ["ln"i rSub { size 8{C2} } - "ln"i rSub { size 8{C1} } right ]= - V rSub { size 8{T} } "ln" \( { {i rSub { size 8{C1} } } over {i rSub { size 8{C2} } } } \) } {} (50)

Collector current iC1iC1 size 12{i rSub { size 8{C1} } } {} is equal to i1i1 size 12{i rSub { size 8{1} } } {}; therefore,

i C1 = i 1 = v i R 1 i C1 = i 1 = v i R 1 size 12{i rSub { size 8{C1} } =i rSub { size 8{1} } = { {v rSub { size 8{i} } } over {R rSub { size 8{1} } } } } {} (51)

Neglecting the transistor base currents, collector current iC2iC2 size 12{i rSub { size 8{C2} } } {} is

i C2 = V R − ( v EB 2 − v EB 1 ) R 2 i C2 = V R − ( v EB 2 − v EB 1 ) R 2 size 12{i rSub { size 8{C2} } = { {V rSub { size 8{R} } - \( v rSub { size 8{ ital "EB"2} } - v rSub { size 8{ ital "EB"1} } \) } over {R rSub { size 8{2} } } } } {} (52)

where VRVR size 12{V rSub { size 8{R} } } {} is a reference voltage. Usually, we assume that

v BE 2 − v BE 1 << V R v BE 2 − v BE 1 << V R size 12{v rSub { size 8{ ital "BE"2} } - v rSub { size 8{ ital "BE"1} } "<<"V rSub { size 8{R} } } {}

therefore,

i C2 = V R R 2 i C2 = V R R 2 size 12{i rSub { size 8{C2} } = { {V rSub { size 8{R} } } over {R rSub { size 8{2} } } } } {} (53)

Input voltage v01v01 size 12{v rSub { size 8{"01"} } } {} to op-amp A2A2 size 12{A rSub { size 8{2} } } {} is now

v 01 = − V T ln ( i C1 i C2 ) = − V T ln [ ( v i R 1 ) ( R 2 V R ) v 01 = − V T ln ( i C1 i C2 ) = − V T ln [ ( v i R 1 ) ( R 2 V R ) size 12{v rSub { size 8{"01"} } = - V rSub { size 8{T} } "ln" \( { {i rSub { size 8{C1} } } over {i rSub { size 8{C2} } } } \) = - V rSub { size 8{T} } "ln" \[ \( { {v rSub { size 8{i} } } over {R rSub { size 8{1} } } } \) \( { {R rSub { size 8{2} } } over {V rSub { size 8{R} } } } \) } {} (54)

Since op-amp A2A2 size 12{A rSub { size 8{2} } } {} is a non-inverting amplifier, we have

v 0 = ( 1 + R 4 / R 3 ) v 0i v 0 = ( 1 + R 4 / R 3 ) v 0i size 12{v rSub { size 8{0} } = \( 1+ {R rSub { size 8{4} } } slash {R rSub { size 8{3} } \) v rSub { size 8{0i} } } } {}

Which becomes

v 0 = − V T ( 1 + R 4 R 3 ) ln [ ( v i R 1 ) ( R 2 V R ) ] v 0 = − V T ( 1 + R 4 R 3 ) ln [ ( v i R 1 ) ( R 2 V R ) ] size 12{v rSub { size 8{0} } = - V rSub { size 8{T} } \( 1+ { {R rSub { size 8{4} } } over {R rSub { size 8{3} } } } \) "ln" \[ \( { {v rSub { size 8{i} } } over {R rSub { size 8{1} } } } \) \( { {R rSub { size 8{2} } } over {V rSub { size 8{R} } } } \) \] } {} (55)

For this circuit, the output voltage is directly proportional to the log of the input voltage. Note that the reverse-saturation currents for the two transistors cancel each other, which was one objective of this circuit. Experimentally, the circuit in Figure 21 performs the log function over approximately four orders of magnitude of the input voltage, generally in the range of 2 mV < vi < 20 V.

To summarize the operation of the circuit in Figure 21, we see from Equation 53 that the collector current iC2iC2 size 12{i rSub { size 8{C2} } } {} is essentially constant. A constant collector current implies a constant B-E voltage, that is, vBE2=constantvBE2=constant size 12{v rSub { size 8{ ital "BE"2} } = ital "cons""tan"t} {}. On the other hand, input current i1i1 size 12{i rSub { size 8{1} } } {} is directly proportional to input voltage vivi size 12{v rSub { size 8{i} } } {} and, since i1=iC1i1=iC1 size 12{i rSub { size 8{1} } =i rSub { size 8{C1} } } {}, collector current iC1iC1 size 12{i rSub { size 8{C1} } } {} is directly proportional to its corresponding input voltage. In this circuit, we apply a collector current iC1iC1 size 12{i rSub { size 8{C1} } } {} and determine the resulting B-E voltage vBE1vBE1 size 12{v rSub { size 8{ ital "BE"1} } } {}. Since vBE2vBE2 size 12{v rSub { size 8{ ital "BE"2} } } {} is a constant, input voltage v01v01 size 12{v rSub { size 8{"01"} } } {} to op-amp A2A2 size 12{A rSub { size 8{2} } } {} is a direct function of vBE1vBE1 size 12{v rSub { size 8{ ital "BE"1} } } {}, which in turn is proportional to the log of the input voltage.