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Inside Collection (Course): Lectures on Analog Electronics
Summary: This gives problems on diffusion capacitances and junction capacitances.
Tutorial 3_supplementary_AE Lecture No.3.
Problems on parasitic capacitances associated with Diode at high frequencies.
Problem 1.Given a diode under reverse bias with a depletion width 4µm.
Absolute permittivity ε0 = 8.854×10-12F/m and relative permittivity or dielectric constant (k) = εr= 11.6 [Answer: 26pF]
Problem 2. A diode is under forward bias condition at VD = 0.7V. Reverse Saturation current IS=16nA at 300K. Minority carrier life time are τn = τp = 25µsec.
Problem 3. A silicon PN junction has doping concentrations NA= 1019/cc & ND= 1015/cc. Cross sectional area A= 0.001cm2. Since it is one sided step junction major role is played by holes injected in N-type region. Hence the life-time of holes is given τp(P region)= 0.3µsec.
Under forward bias condition of VD = 0.6V , determine:
Solution: Here ID is not given nor the saturation current IS is given. We can use the doping to find either of the two.
ID = Qp/τp and
Qp= charge stored in N region under forward biased condition =
q{pn(0)-pn(thermal equilibrium)}LpA;
and Lp=√(Dpτp) and Dp = µ×VT = 450 cm2/(V-sec)×26mV= 11.7 cm2/sec;
Therefore Lp= 1.94×10-3 cm.
Therefore ID= q{pn(0)-pn(thermal equilibrium)}LpA/τp = 2.453mA;
Therefore rd = 26mV/2.453mA =10.59 Ω.
rd×Cd= τp therefore Cd =28,000pF.
Calculation of CjD:
CjD= εA/dn where dn = the depletion width on N-side = √(qεND/2)√(øB0-VF);
In a one sided step junction d~ dn ( depletion width on the lightly doped side);
Therefore CjD= εA/[√(qεND/2)√(øB0-VF)] = √(2ε/(qND))×(1/√( øB0-VF));
øB0 = Built in barrier potential under zero bias condition= VTln(NAND/ni2)=817.056mV;
Therefore CjD= 19.8 pF.
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Last edited by Bijay_Kumar Sharma on Jul 30, 2009 7:18 am -0500.
