The increasing variability present in modern CMOS devices demands revolutionary changes in the design methodology, algorithms and tools used to produce integrated circuits and systems. Progressive scaling of CMOS transistors has driven the success of the global semiconductor industry, as captured by the reknowned Moore’s Law which stipulates an exponential increase of the number of transistors in chips, with some modern chips now comprising several billion transistors. Until recently the transistors in silicon chips were assumed to be of uniform design, having identical physical properties and characteristics. However as illustrated in Figure 1, as transistor dimensions approach the nanometer scale this assumption no longer holds true with microscopic differences in atomic structure, doping configuration and material granularity producing differences in the macroscopic behaviour of individual devices.

As a result Moore’s Law as tracked by the International Technology Roadmap for Semiconductors (ITRS) is now reaching the physical, atomistic limits of silicon and radical new approaches are needed that encompass this atomistic variability. To address this problem, it is now widely recognized that a paradigm shift must happen in circuit and system design. Strong links have to be established between system, circuit and fundamental device technology research in order to allow modern integrated circuits to cope with the statistically varying behaviour of individual transistors on a chip. Design methods must evolve to accommodate the increasing statistical variability of transistors and absorb the impact that this can have on circuit and system performance. The nanoCMOS project confronts these engineering challenges. This chapter introduces the project in detail and concludes with a brief look at future work in this area.

Figure 1: Origin of atomic scale variability in nano CMOS transistors

Changing design rules for new device architectures and device variability adds significant complexity to the design process, requiring the orchestration of a broad spectrum of tools by geographically distributed teams of device experts, circuit and system designers. In the nanoCMOS project the challenges that this working method presents are being addressed by embedding e-Science technology and know-how in the device modeling and design groups and changing the ways in which these disparate groups currently work. The nanoCMOS project was funded for 4 years and started in October 2006. It involves collaboration between world leading device modelling and circuit and system design research groups at the universities of Glasgow, Edinburgh, Manchester, Southampton and York. This academic grouping is enhanced by strong links and collaboration with industrial partners including leading semiconductor, EDA tool vendors and design companies such as Freescale, Fujitsu, National Semiconductor, Synopsis, ARM, Wolfson Microelectronics amongst others. The project will provide valuable insights for industry on the challenges faced in the nanoCMOS domain and how the global semiconductor industry can address them.

In order to study the statistical fluctuations introduced by the discreteness of charge and matter it is necessary to perform 3D simulations of very large ensembles of hundreds of thousands of devices, rather than a single representative device. Given the increasing number of transistors in modern chips, simulation of very large statistical samples of devices is required to allow statistically rare devices with potentially fatal effects on circuit performance and functionality to be examined. This requires access to significant distributed high performance computing resources, including the UK e-Science National Grid Service, ScotGrid and a wide variety of other resources including Condor pools and campus clusters across partner sites. However, this is not simply another large scale simulation problem, since the commercially sensitive nature of the information and stringent IP protection requirements necessitate fine grained security on access to, and usage of, licensed software; protection of the intellectual property associated with circuit and device designs, data and simulations belonging to industrial partners and key stakeholders.

To this end, the project has developed an infrastructure capable of providing comprehensive security. This includes exploitation of Kerberos for secure global file based access through the Andrews File System; authorization technologies such as PERMIS for definition and enforcement of access policies using centralized attribute authorities such as the Virtual Organisation Membership Service (VOMS), and simple user-oriented access to a project portal through the Internet2 Shibboleth technology using the UK Access Management Federation. Furthermore, the project has identified that a key challenge is in data annotation and management. The simulations that are undertaken can generate large quantities of data and meta-data and the electronics domain unlike other domains does not have agreed standards on data format, rather, the data formats tend to be driven by commercial tool providers.

Figure 2: nanoCMOS Resource Usage on ScotGrid

(a) Total CPU time per VO between 16.11.2006 and 19.3.2009 (b) Total number of submitted jobs per VO between 16.11.2006 and 19.3.2009

Traditionally, due to the computational complexity of 3D device simulation, studies of variability have been based on small ensembles of devices typically up to 200 devices and simulations on much larger scale have hitherto never been undertaken. Simulations of ensembles of up to 100,000+ devices enabled by the grid technology are shedding new light on the impact of atomic structure variation on the behaviour of devices, especially at the extreme limits of device variability. Furthermore, based on these simulations, we have been able to examine the effect of device variability at a simple circuit level and have simulated over 1 million CMOS inverters using random configurations of devices. Figure 3(a) shows the potential and dopant position of a statistically rare device. Figure 3(b) shows the threshold voltage variation as a function of the number of dopants.

Figure 3

(a) Potential/Dopant Distribution for Statistically Rare Device (b) Threshold Voltage Variation as Function of the Number of Dopant atoms in the transistor

The nanoCMOS project has shown the value of e-Research methods in the field of microprocessor circuit design. Use of distributed high performance computing and other dispersed computing resources has allowed for large scale simulations that assist the CMOS design community in managing device variability. The work on nanoCMOS is still progressing and higher level circuit and system design tools are being incorporated into the e-Infrastructure. The systems are being extended in numerous other ways including seamless access to multiple-HPC facilities depending upon user privileges. Optimisation of job submission and management based upon data distribution and security constraints is another area that is currently being investigated. More information on the nanoCMOS project is available at www.nanocmos.ac.uk, or through contacting Prof. Asenov (a.asenov@elec.gla.ac.uk - science related questions) or Prof. Sinnott (r.sinnott@nesc.gla.ac.uk - e-Infrastructure related questions).

This work was funded by a grant from the UK Engineering and Physical Sciences Research Council. We gratefully acknowledge their support.

Sinnott, R.O. et al. (2006). Meeting the Design Challenges of nanoCMOS Electronics: An Introduction to an EPSRC Pilot Project. UK e-Science All Hands Meeting, Nottingham UK, September.

Reid, D. et al. (2008). Prediction of Random Dopant Induced Threshold Voltage Fluctuations in NanoCMOS Transistors International Conference on Simulation of Semiconductor Processes and Devices, Sept.