Appendix III

Five Alternatives of Next Generation Lithography

[“Next Generation Lithography”by Eric J. Lerner, June 1999,American Institute of Physics,pp 18 to 21.]

In four decades following the invention of IC chip, speed has doubled every 3 years and smallest feature size has scaled down by 2 every 6 years in accordance with Moore’s Law. This accounts for half the increase in Instruction per second executed by a given Computer of a given technology. The other half of the increase in IPS(instruction per second) has come about by the improvement in the architecture of microprocessor chip. Von Neumann sequential architecture has evolved into parallel architecture such as pipelining, systolic and data flow architecture. This has enabled to carry out complex instruction in reduced number of machine cycles. With the downward scaling of the devices, the clock speed has increased and simultaneously the number of machine cycles utilized to carry out an instruction has decreased. Both these factors increase the computational speed of a given computer of a given technology.

As devices have been scaled down, the line width has decreased. This has required that the wavelength of the light used in the photo-lithography is correspondingly decreased according to the formula:

W = minimum feature size=(according to Rayleigh Equation)=k.λ/(NA)

where NA(numerical aperture)=n.Sin(α) = d/(2f);

n= index of refraction of the medium surrounding the lens and α = acceptance angle of the lens system;

d= aperture diameter and f = focal length.

k= resolution factor.

Lithography underlies the entire I.C. technology. I.C chips are created by alternatively etching the oxide layer and creating a window pattern, through the window pattern carrying out the diffusion of dopents or implanting the dopents. Etching out a window pattern involves a pattern of photo resist imprinted on the chip through Photo Lithography Technique. The photo-lithography involves masks. Masks consist of chromium lines laid on quartz substrate. They are generated by computer controlled electron beams which lay down the pattern of chromium lines. The masks are 4 times larger and wider than the circuit pattern actually required. By optical projection the mask pattern is reduced 4 times to the correct size. This enables the mask generation more accurate and technically viable. In the mask the minimum feature size is 4 times the actual size.

Below 30nm we have to go for Next Generation Lithography. The five alternatives are:

The equipment set-up has been described in Part 3 of the main text in Figure 3 . The description of the setup is as follows:

Laser produced plasma

↓ radiation

Irradiates the supersonic jet of Xenon Gas

↓reradiates

EUV(13.4nm equivalent to 100eV energy)

↓

Complex Optical System

↓

Through the optical system, EUV is reflected to Reflective Mask with pattern

↓

From the Reflective Mask, EUV is reflected to the substrate’s photo resist coating with 4 times reduction creating the correct size chip pattern in the photo resist for further processing

Here the wavelength used is Soft X-Ray of wave length one order of magnitude lower i.e. of 1.34nm = 13.4A° (1000eV)

Synchrotron Radiator is used as X-Ray Source

↓

Thin stripes of radiation generated

↓

The stripe of radiation is bounced off a low-incidence angle oscillating mirror

↓

Bounced off beam is scanned across the mask area

↓

Chip pattern is imprinted on the Photo Resist coating of the wafer

Here the mask pattern is of the same size as that of the pattern imprinted on the wafer. Mask is made of SiC , 2µm thick and 5 cm wide. The mask is kept thin to make it transparent to Soft X-Ray. These are fragile and because the mask pattern is of the same size as the actual pattern hence electron beam generation of the pattern on the mask becomes difficult. Soft X-Ray has deeper penetrating power hence existing photo-resist suffice X-Ray proximity lithography requirement.

Electron’s wave-particle duality allows its wave nature to be utilized for electron beam lithography where electron wave corresponds to a wave length λ. This wavelength is determined by its linear momentum p = mv.

From deBroglie wave particle duality: λ = h/p = h/ (mv);

If an electron beam is accelerated through 100kV it acquires a kinetic energy of 100keV.

Therefore (1/2)mv² = 100kev = (100×10³×q)

Therefore mv = √(200×10³×q×m) where m = mass of an electron.

Therefore λ = h/[√(200×10³×q×m)]

Substituting the numerical values of h, q and m:

λ = 3.9 pico meter.

This wave length is more than sufficient for resolving features of nm size. By using differentially scattered electron beam, electrons through the transparent area exposes the photo resist whereas in pattern area the electron beam is prevented from transferring its energy to the photo resist. This system is called “Scattering with angular limitation projection electron beam lithography” known by its acronym “SCALPEL”. Diagram Figure III.1 describes the SCALPEL system.

Here 4-to-1 reduction is allowed hence the mask is conveniently generated but fragility of the mask remains a problem.

This is the least developed of all the NGL. It uses accelerated hydrogen or helium ions instead of electrons and focuses them using electrostatic field. This has a mask which has holes punched for allowing the ions to pass through. The holes are the transparent equivalent of the conventional optical masks. Hence this is stencil like mask. The stencil mask does not allow closed path of conductors . This is the donut problem.

Next step in Moore’s scaling aims at 100nm and 70 nm generation chips. Here Excimer Laser source also known as Flouride Lasers will generate 157nm monochromatic light. Calcium Fluoride lenses could be used for focusing. Resolution enhancement could make optical lithography viable for 100nm and 70nm generation chips.

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Last edited by Bijay_Kumar Sharma on Jan 10, 2010 5:17 am -0600.