We now move on to another three terminal device - also called a transistor. This transistor, however, works on much different principles than does the bipolar junction transistor of the last chapter. We will now focus on a device called the field effect transistor, or metal-oxide-semiconductor field effect transistor or simply MOSFET.

In Figure 1 we have a block of silicon, doped p-type. Into it we have made two regions which are doped n-type. To each of those n-type regions we attach a wire, and connect a battery between them. If we try to get some current, I, to flow through this structure, nothing will happen, because the n-p junction on the RHS is reverse biased, i.e., the positive lead from the battery going to the n-side of the p-n junction. If we attempt to remedy this by turning the battery around, we will now have the LHS junction reverse biased, and again, no current will flow. If, for whatever reason, we want current to flow, we will need to come up with some way of forming a layer of n-type material between one n-region and the other. This will then connect them together, and we can run current in one terminal and out the other.

To see how we will do this, let's do two things. First we will grow a layer of SiO₂ (silicon dioxide or silica, but actually refered to as "oxide") on top of the silicon. To do this the wafer is placed in an oven under an oxygen atmosphere, and heated to 1100 °C. The result is a nice, high-quality insulating SiO₂ layer on top of the silicon). On top of the oxide layer we then deposit a conductor, which we call the gate. In the "old days" the gate would have been a layer of aluminum; hence the "metal-oxide-silicon" or MOS name. Today, it is much more likely that a heavily doped layer of polycrystalline silicon (polysilicon, or more often just "poly") would be deposited to form the gate structure. Polysilicon is made from the reduction of a gas, such as silane (SiH₄), Equation 1.

The silicon is polycrystalline (composed of lots of small silicon crystallites) because it is deposited on top of the oxide, which is amorphous, and so it does not provide a single crystal "matrix" which would allow the silicon to organize itself into one single crystal. If we had deposited the silicon on top of a single crystal silicon wafer, we would have formed a single crystal layer of silicon called an epitaxial layer. This is sometimes done to make structures for particular applications. For instance, growing a n-type epitaxial layer on top of a p-type substrate permits the fabrication of a very abrupt p-n junction.

Now we can go back now to our initial structure, shown in Figure 1, only this time we will add an oxide layer, a gate structure, and another battery so that we can invert the region under the gate and connect the two n-regions together. Well also identify some names for parts of the structure, so we will know what we are talking about. For reasons which will be clear later, we call the n-region connected to the negative side of the battery the source, and the other one the drain. We will ground the source, and also the p-type substrate. We add two batteries, Vgs Vgs between the gate and the source, and Vds Vds between the drain and the source.

It will be helpful if we also make another sketch, which gives us a perspective view of the device. For this we strip off the gate and oxide, but we will imagine that we have applied a voltage greater than VT VT to the gate, so there is a n-type region, called the channel which connects the two. We will assume that the channel region is LL long and WW wide, as shown in Figure 3.

Next we want to take a look at a little section of channel, and find its resistance ⅆ⁢R ⅆ R , when the little section is ⅆ⁢x ⅆ x long, Equation 2.

We have introduced a slightly different form for our resistance formula here. Normally, we would have a simple σσ in the denominator, and an area AA, for the cross-sectional area of the channel. It turns out to be very hard to figure out what that cross sectional area of the channel is however. The electrons which form the inversion layer crowd into a very thin sheet of surface charge which really has little or no thickness, or penetration into the substrate.

If, on the other hand we consider a surface conductivity (units: simply mhos), σs σs , Equation 3, then we will have an expression which we can evaluate. Here, μs μs is a surface mobility, with units of cm²/V.sec, that is the quantity which represented the proportionality between the average carrier velocity and the electric field, Equation 4 and Equation 5.

The surface mobility is a quantity which has to be measured for a given system, and is usually just a number which is given to you. Something around 300 cm²/V.sec is about right for silicon. Qchan Qchan is called the surface charge density or channel charge density and it has units of Coulombs/cm². This is like a sheet of charge, which is different from the bulk charge density, which has units of Coulombs/cm². Note that:

It turns out that it is pretty simple to get an expression for Qchan Qchan , the surface charge density in the channel. For any given gate voltage Vgs Vgs , we know that the charge density on the gate is given simply as:

However, until the gate voltage Vgs Vgs gets larger than VT VT we are not creating any mobile electrons under the gate, we are just building up a depletion region. We'll define QT QT as the charge on the gate necessary to get to threshold. Q T = c ox ⁢ V T Q T c ox V T . Any charge added to the gate above QT QT is matched by charge Qchan Qchan in the channel. Thus, it is easy to say: Equation 8 or Equation 9.

Thus, putting Equation 8 and Equation 3 into Equation 2, we get:

If you look back at Figure 2, you will see that we have defined a current Id Id flowing into the drain. That current flows through the channel, and hence through our little incremental resistance ⅆ⁢R ⅆ R , creating a voltage drop ⅆ⁢ V c ⅆ V c across it, where Vc Vc is the channel voltage, Equation 11.

Let's move the denominator to the left, and integrate. We want to do our integral completely along the channel. The voltage on the channel V c ⁢x V c x goes from 0 on the left to Vds Vds on the right. At the same time, xx is going from 0 to LL. Thus our limits of integration will be 0 and Vds Vds for the voltage integral ⅆ⁢ V c ⁢x ⅆ V c x and from 0 to LL for the xx integral ⅆ⁢x ⅆ x .

Both integrals are pretty trivial. Let's swap the equation order, since we usually want Id Id as a function of applied voltages.

We now simply divide both sides by LL, and we end up with an expression for the drain current Id Id , in terms of the drain-source voltage, Vds Vds , the gate voltage Vgs Vgs and some physical attributes of the MOS transistor.

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This work is licensed by Andrew R. Barron under a Creative Commons Attribution License (CC-BY 3.0), and is an Open Educational Resource.

Last edited by Andrew R. Barron on Feb 9, 2010 9:24 pm -0600.