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EC1561_Syllabus of Digital System Design using VHDL

Module by: Bijay_Kumar Sharma. E-mail the author

Summary: EC1561 is an elective offered to students of ECE Department of NIT,Patna, at 3rd Year Level.

EC1X66 [3-1-0]

Digital Systems Design using VHDL 

Pre-requisite: EC1303[3_0_3]Digital Electronics

Historical Background of Integrated Circuit Technology- Evolution of IC Chips in terms of packing density, clock speed; Computer Aided Design of IC Chips, Moore’s Law. [4L]

Introduction to Digital System Design- Simple Programmable Logic Devices(SPLD), Complex Programmable Logic Devices(CPLD), Field Programmable Gate Array(FPGA), Application Specific Integrated Circuit(ASIC); [8L]

Basics of VHDL-VHDL: An Introduction , Why VHDL, Characteristics , Basic Structure , Data Objects, Data Types, Combinational Logic Statements, Sequential Logic Statements, Concurrent Statements, Function, Procedure, Packages, Configurations. [10 L]

Implementation of Logic Design (both combinatorial and sequential) using VHDL. Validation of Logic Design using Test Benches. [10L]

Moore and Mealy State Machine,Moore and Mealy variants, output of state machine, Moore Machine with clocked outputs, Mealy Machine with clocked outputs, state coding, residual states,optimum state machine in VHDL, asynchronous state machine [10L].Total 42 Lectures + 14 hours tutorial[Hand on practice on Xilinx and ModelSim].

Text Book: VHDL for Engineers, Kenneth Short, Perason.

Reference Books:

  1. VHDL for Designers, Stefan Sjoholm & Lennart Lindh, Prentice Hall.
  2. Principles of Digital System Design using VHDL, Roth John, CENGAGE Learning,2010.

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