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DSD_Chapter 2_Basics of PLDs

Module by: Bijay_Kumar Sharma. E-mail the author

Summary: DSD_Chapter 2 explains how a ROM can be used as Boolean Function Generator.

Digital System Design_Chapter 2_Basic Philosophy of Simple Programmable Logic Devices(SPLD).

In Chapter 1_ Part 2 we saw that PLAs, PALs, GALs, PLDs and PROM are collectively called Simple Programmable Logic Devices. Here we will examine PLA, PAL and PROM closely to understand how exactly Sum of Products Boolean Function is achieved.

CODE CONVERTERS- DECODER & ENCODER.

All these programmable devices are based on the philosophy of M-bit Code Input being converted to N-bit Code output.

2M = µ and 2N = α.

Here α may be less than µ. In that case each of the M-bit code does not have a corresponding unique N-bit code. Many of the M-bit codes may have the same N-bit code.

How does the code converter work:

The figure 1 gives the code converter working.

Figure 1
Figure 1 (Picture 1.png)

Figure 1. Code-converter System.

ROM is typical Code Converter system.

Here M-bit decoder is AND system and N-bit encoder is OR system.

Therefore:

Each bit-line Yi = SUM of PRODUCT of X0,X1,X2…..X(m-1).

Decoder Word Line generates PRODUCT terms.

A DECODER is realized by Multiplexer also known as MUX. MUX is nothing but a combination of AND gates. In Figure 2 we show a 4-bit binary to decimal decoder:

Figure 2
Figure 2 (Picture 2.png)

Figure 2. 4-bit binary to decimal decoder.

Figure 3
Figure 3 (Picture 3.png)

Figure 3. Block Model of 4-bit binary to decimal decoder.

Table 1. Truth Table of the decoder

Table 1
D C B A Word Line Decoded Decimal Value
0 0 0 0 W0 0
0 0 0 1 W1 1
0 0 1 0 W2 2
0 0 1 1 W3 3
0 1 0 0 W4 4
0 1 0 1 W5 5
0 1 1 0 W6 6
0 1 1 1 W7 7
1 0 0 0 W8 8
1 0 0 1 W9 9

In Figure 3, for every BCD code one of the 10 Word lines will go HIGH and the remaining lines will be LOW. Figure 2 tells us that every Word Line is a PRODUCT of 4 Variables A,B,C,D and their complements A′ , B′,C′,D′ .

Encoder Bit Line is SUM of Words.

Keyboard of a Computer generates 8-bit ASCII Code on pressing one of the keys. Hence Keyboard is ENCODER ARRAY. For simplicity of presentation we present 10Key - 4bit Encoder. The customer will have to decide and specify the 4-bit codes corresponding to 10 keys. That is the Customer will provide the Truth Table.

Suppose the customer provides the following Truth Table 2:

Table 2. The Truth Table of the Encoder.

Table 2
W9 W8 W7 W6 W5 W4 W3 W2 W1 W0   Y3 Y2 Y1 Y0
0 0 0 0 0 0 0 0 0 1   0 0 0 0
0 0 0 0 0 0 0 0 1 0   0 0 0 1
0 0 0 0 0 0 0 1 0 0   0 0 1 0
0 0 0 0 0 0 1 0 0 0   0 0 1 1
0 0 0 0 0 1 0 0 0 0   0 1 0 0
0 0 0 0 1 0 0 0 0 0   0 1 0 1
0 0 0 1 0 0 0 0 0 0   0 1 1 0
0 0 1 0 0 0 0 0 0 0   0 1 1 1
0 1 0 0 0 0 0 0 0 0   1 0 0 0
1 0 0 0 0 0 0 0 0 0   1 0 0 1
Figure 4
Figure 4 (Picture 4.png)

Figure 4. 10 Key to 4-bit Encoder Array.

Here the Word line (rows) is crossing the bit-line.

If W1 is pressed, 5V is applied to the corresponding Word line or to the corresponding ROW. The Row crosses the four bit-lines at the four intersections. Which ever intersection is shorted on that bit line ‘1’ is generated as seen in Figure 4. Where intersections are not shorted there we get ‘0’ on the bit line. For W1, Y3=0,Y2=0,Y1=1, Y0 = 0 binary code is generated as desired by the customer.

For W6, 0-1-1-0 is generated. Now let us examine the bit lines:

Y0 is HIGH if W1 is pressed or W1 is HIGH or W3 is HIGH or W5 is HIGH or W7 is HIGH or W9 is HIGH.

Therefore Y0 = W1 + W3 + W5 + W7 + W9;

Similarly Y1 = W2 + W3 + W6 + W7;

Similarly Y2 = W4 + W5 + W6 + W7;

Similarly Y3 = W8 + W9;

If we combine the Word-Line and bit-line we get:

Y0 = D′C′B′A + D′C′BA + D′CB′A + D′CBA + DC′B′A;

Y1= D′C′BA′ + D′C′BA + D′CBA′ + D′CBA;

Y2= D′CB′A′ + D′CB′A + D′CBA′ +D′CBA;

Y3 = DC′B′A′ + DC′B′A;

Thus we have achieved 4 Sum-of-Product(SOP) Boolean Functions. By combining Decoder-Encoder we achieve AND-OR function which is the same as NAND-NAND function.

Figure 5
Figure 5 (Picture 5.png)

Figure 5. The combination of Decoder-Encoder is AND-OR gate.

The above circuit is Programmable Logic Array.

The AND terms are generated by shorting the A,B,C,D and A′, B′, C′, D′ lines or Columns with the Rows of Input of Ten AND gates.

The OR terms are generated by shorting the intersection of Word-line(rows) and bit-lines(columns)

The shorting of intersection can be done putting a DIODE from the Word-line to bit-line as shown in Figure 6.

The shorting of intersection can be done by using multi-emitter BJT as shown in Figure 7.

The shorting of intersection can be done using NMOS as shown in Figure 8.

Figure 6
Figure 6 (Picture 6.png)

Figure 6. Diode Matrix is used to generate OR terms.

Diodes are the memory elements. Diode transfers ‘1’ of Word-line to the corresponding Bit-line. The output WORD for any input code may be read as many times as possible. But the stored relationship between Input Code and Output Word cannot be modified. The Diode Matrix is fabricated at the factory level. Hence this is Read-Only-Memory (ROM).

Figure 7
Figure 7 (Picture 7.png)

Figure 7. Multiemitter BJTs are used for transferring ‘1’ from Word-line to Bit-line with which the intersection is shorted.

Multiemitter BJT has four emitters. When an Emitter is shorted to Bit-line, BJT behaves like Emitter Follower and as soon as the WORD-line goes HIGH the shorted bit-line ( shorted with the given high Word-line) goes HIGH and all other bit-lines remain LOW.

According to customer requirement, the manufacturer shorts or opens the intersection by the use of proper MASK. This is Custom Programming or Mask Programming or Hardware Programming. This is ‘One-Time Factory Programming’.

WORKING OF 4k-bit Static ROM.

Static ROMs can be built of BJT or NMOS. These have no clock input. These are non-volatile. They never lose data. They are available in 1 to 64kb range. NMOS StaticROM have access time 0.1 to 1 µsec. This access time is one order of magnitude longer than that of BJT StaticROM.

In a NMOS or BJT StaticROM we have a DECODER as shown in Figure 8. It has address input or select input. In this case address word is 10-bit wide. Hence it can access 1024 locations of memory. At every location a 4-bit wide binary word can be stored as shown in Figure 9. When an address word arrives , one of the 1024 Word-lines goes HIGH. At any instant only one Word-line can go high.

Figure 8
Figure 8 (Picture 8.png)

Figure 8. Decoder for 4k-bit ROM.

Figure 9
Figure 9 (Picture 9.png)

Figure 9.An NMOS ROM encoder ( Only 5 of the 1024 Word-lines are shown). Small circle means the intersection is shorted.

In Figure 8, when the following address word is applied:

Table 3
B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
0 0 0 0 0 0 0 0 0 0

Then W0 line goes HIGH. This selects the DATA WORD ‘0110’ in Figure 9.

Let us examine Figure 9 closely:

Q3 and the NMOSs in that ROW are Load FETs. Here Drain and Gate of NMOS have been shorted. Hence Q3 and its corresponding elements act as loads of the bit-lines Y0,Y1,Y2,Y3.

NMOS has the advantage that it can act in following manners:

  1. as a Capacitor when you operate between Gate and Source;
  2. as three terminal active element;
  3. as a non-linear two terminal resistance when Gate and Drain are shorted together.

NMOSs in the Word-lines act as MEMORY ELEMENTS.

All Bit-lines are at HIGH level. Because Vdd = 5V is being applied to all Bit-lines and all bit-lines at the other end is simply hanging.

When W0 goes HIGH, the intersections of Y1, Y2 and W0-line have no NMOS. Y1 = ‘1’ and Y2 = ‘1’ state continues as it was before.

At the intersection of Y0 and Y3 we have Q2 and Q4 NMOSs. Their Gates are connected to W0-line which is presently held HIGH at 5V > Threshold Voltage of NMOS. Hence Q2 and Q4 turn ON and provide a short to Ground. Therefore Y0 = ‘0’ and Y3= ‘0’.

Here we are following ACTIVE-LOW Logic. Ordinarily bit-lines are at ‘1’ and when ACTIVE they go LOW or go to ‘0’.

Thus with 0000000000 address word applied to the address bus of the given ROM, W0 gets selected and ‘0110’ ,which is stored in the ROM memory space, gets READ out.

The following Table 1 gives the binary bits stored in locations selected by W0,W1,W2 and W500 word-lines.

Table 1. The Word address and the bit-outputs.

Table 4
B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 WORD-line Y0′ Y1′ Y2′ Y3′
0 0 0 0 0 0 0 0 0 0 W0 0 1 1 0
0 0 0 0 0 0 0 0 0 1 W1 1 0 0 1
0 0 0 0 0 0 0 0 1 0 W2 0 1 0 1
0 1 1 1 1 1 0 1 0 0 W500 1 1 0 0

Here the Bits stored are pre-programmed and cannot be changed unless we find some methods to construct NMOS and omit NMOS at the 1024×4 ROM Memory Cells.

What we have shown is a Factory programmed ROM. Field programmed ROM had to wait for several years before it was introduced as Field Programmable Devices.

In the above example Y0 bar or Y0′ = W0 +W2;

Y1′ = W1; Y2′ = W1 + W2 + W500; Y3’ = W0 + W500;

By inverting the bit-lines we obtain SOP Logic Functions.

ROMs do not minimize the gates for a given CODE-conversion.

Suppose the customer wants me to design ‘BCD to 7-Segment decoder-driver’.

What this means that :

Table 2. Decoding of BCD to Decimal NUMERIC value.

Table 5
BCD code Decimal Number to be displayed on 7-Segment display
0000 0
0001 1
0010 2
0011 3
0100 4
0101 5
0110 6
0111 7
1000 8
1001 9

In Figure 10 we have shown the construction and the composite structure of 7-SEGMENT DISPLAY. In Figure 10 it is also shown as to which LED should glow corresponding to a decimal value. From this knowledge we can construct the following Table 3 for code conversion.

Figure 10
Figure 10 (Picture 10.png)

Figure 10. Construction of Common Anode 7-Segment Display.

Table 3. Conversion from a BCD to a Seven-Segment-Display Code.

Table 6
BCD code Word-line Y6 Y5 Y4 Y3 Y2 Y1 Y0
DCBA   g′ f′ e′ d′ c′ b′ a′
0000 W0= D′C′B′A′ 1 0 0 0 0 0 0
0001 W1= D′C′B′A 1 1 1 1 0 0 1
0010 W2= D′C′BA′ 0 1 0 0 1 0 0
0011 W3= D′C′BA 0 1 1 0 0 0 0
0100 W4= D′CB′A′ 0 0 1 1 0 0 1
0101 W5=D′CB′A 0 0 1 0 0 1 0
0110 W6= D′CBA′ 0 0 0 0 0 1 1
0111 W7= D′CBA 1 1 1 1 0 0 0
1000 W8= DC′B′A′ 0 0 0 0 0 0 0
1001 W9= DC′B′A 0 0 1 1 0 0 0

Since input code is 4 bits therefore there are 24 = 16 word lines hence Table 3 must have 6 extra Word-lines i.e. W10, W11, W12, W13, W14, W15. Corresponding to these 6 Word-lines there are some arbitrary SYMBOL displays depending upon the convenience of the Designer.

If all 16 Word-lines are considered then the bit-line Y0 will be by inspection of the Table:

Y0= W1 + W4 + W6 + W10 + W11 + W14 + W15;

By replacing the Word-line by their corresponding Product Term we get:

Y0 = D′C′B′A + D′CB′A′ + D′CBA′ + DC′BA′ + DC′BA + DCB′A′ + DCBA′ + DCBA.

By minimization technique we obtain:

Y0 = D′C′B′A + CA′ + DB;

Similarly minimized expressions can be obtained for all the remaining 6 bit-lines.

If using the minimized expressions for Y0, Y1, Y2, Y3 Y4, Y5, Y6 we build the decoder-driver then almost 20% saving in component count takes place as compared to a decoder-driver built by ROM. It can be even more. But this will require extra man-hours for minimizing and designing. If the demand can justify this extra cost then one could go for these especially designed and optimized circuits. These circuits are called ‘Application Specific Integrated Circuits’(ASIC). The ‘BCD to 7 Segment decoder-driver’ presently available in the market by the component code 74HC4511 is one such ASIC circuits.

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