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Course by: Bijay_Kumar Sharma. E-mail the author

Digital System Design_Chapter 2_Section 2_Wishlist of Digital System Designer.

Module by: Bijay_Kumar Sharma. E-mail the author

Summary: DSD_Chapter 2_Section 2 describes the technological development which led to the realization of Electrically Erasable Programmable ROM. EEPROM became the basis of SPLD,CPLD,FPGA.

Digital System Design_Chapter 2_Section 2_Wishlist of Digital System Designer.

The wishlist of Digital System Designer is to create a PLD where he downloads a programme and gets the PLD configured for a certain number of functions. With passage of time a few more functions are to be added and some existing functions are to be omitted. He would like to modify his programme and reload it on the same PLD. Economy-wise this would make sense. But this requires that he has Electrically Erasable and Reprogrammable PLD. This requires that it should be field-programmable.

In 1956, at the request of US Air-Force, Scientists of ARMA Division of American Bosch Arma Corporation, Garden City, New York, developed a User Programmable ROM akin to Diode Matrix shown in Figure 6 of Chapter 2_Section 1. The fresh ROM had a diode connected at all intersections. It implied state HIGH or ‘1’ in all memory cells. The user could retain or omit the DIODE at the intersection as his design need be. By applying a High Voltage Pulse of 30V which is not used in Digital Systems, the user could burn the whiskers of the Diode and thereby “burn” / “Zap” / “blow” open the given diode. This would give ‘0’ state in that particular Memory Cell which lies at the given intersection. This way by burning the requisite set of memory elements namely the diodes at the intersections, the desired functional relationship can be achieved. Once the requisite diodes are blown out, the functional relationship is unalterable. Hence this was called One-Time User Programmed ROM.

In1971, Intel Scientists at Santa Clara, California, developed Erasable Programmable ROM (EPROM). This new device was based on a special double-gate NMOS referred to as Floating-Gate Avalanche-Injection MOS(FAMOS). This double-gate NMOS is shown in Figure 11.

Figure 11.Floating Double Poly-silicon gate structure NMOS used in EPROM

In Figure 9 of Chapter 2_Sec 1, we place such Double-Gate NMOS at all intersections as shown in Figure 12.

Figure 12. EPROM using Double-Gate NMOS.

Before user programming, FAMOS (Double-Gate NMOS) is present at all intersections. Any Word-line going HIGH will place 0s at all the four Bit-lines. Hence effectively EPROM comes with 0s stored in all memory cells. When the user applies 25V pulse between Gate2 and Drain, a high electric field is created in the depletion region of the p-n junction of the Drain-substrate. This electric field is in excess of the critical field. This results in Avalanche Breakdown. This creates a large reverse current. The electron component of this breakdown current is accelerated towards Gate2. It penetrates the thin oxide region and gets accumulated on Gate1. Gate 1 effectively becomes negatively charged hence 5V at Gate2 is no more able to turn this transistor ON. Hence effectively the NMOS at that intersection is disabled and state ‘1’ is permanently stored in that cell. Thus by application of 25V at the requisite intersections’ FAMOS, the transistor is disabled and state ‘1’ is permanently stored giving rise to the desired Boolean Function. Because of SiO2, charges accumulated on Gate2, do not discharge for 10years and longer. The ‘1s’ stored by application of 25V at Gate2s can be easily erased by exposing the ROM to Ultra-Violet light. UV light makes the SiO2 slightly conducting thereby providing a path for leakage of charge accumulated on Gate1. Thus all disabled NMOSs are enabled and this restores EPROM to all ‘0s’ states . This can once again be reprogrammed and reconfigured. But this requires long exposure time in excess of 2 minutes for complete eraser. Hence Electrically erasable and programmable ROM(EEPROM) became the need of the hour.

In 1978, once again the Scientists of INTEL developed and commercialized EEPROM. They reduced the thickness between Gate1 and Channel from 1000A° (100nm) to 100A° (10nm). Now 10V electric voltage pulse was sufficient to writ ‘1s’ in a given cell. The same voltage reversed could erase ‘1’ and reset the whole ROM to ‘0s’.

Thus we see the Digital Designer’s wish list was fulfilled. Now he had a ROM which could be reprogrammed and reconfigured umpteen times as the need arose.

In the following Table 4 we tabulate the chronological development in the field of PLD devices with particular reference to Company ALTERA.

Table 4. Chronological development in the field of PLDs as given by ALTERA.

 Year Products first commercialized. 1984 First PLD in the marketFP300, 320 gates, 3µmCMOS,10MHz, 20 I/O pins 1985-87 TTL libraries for PLDEP 1200 First High Density PLD.EPB 1400 Embedded PLD 1989 Hardware description language introduced 1991 Complex Programmable Logic Devices 1992 SRAM FPGA introduced. 1993-94 Low Power 150MHz CPLD, 3.3V, 12000Gates 1995 First FPGA with embedded RAM100k gates, 0.4-0.3µm technology,> 10M components, 50-100Mhz, First PCI integratedPCI(Peripheral Component Interconnect) 1996-98 SOPC(system on a programmable chip) 1999 First FPGA with high speed input.1.5MGates equivalent to 100M transistors,First embedded CAM(Computer Aided Manufacturing)Fully integrated EDA Flow in Quartus Development Tools 2000-2001 First embedded FPGAWorld’s first soft core microcontroller 2002-2003 0.13µm World Class Products;StratixTM High Density Performance Leader;Stratix GX 10G embedded ?CycloneTM World’s lowest cost FPGA Family.

With Technology improvement, gate count density has continuously inproved.

Table 5. 90nm Technology, 300 mm die size, normalized to 4M gates , 4Mbit Memory.

 Process 0.35µm 0.25um 0.18µm 0.15µm 0.13µm 0.09µm Gate count 500k 1.5M 2.5M 4M 6.5M 10M Wafer Φ 150mm 200mm 200mm 200mm 200mm 300mm Die Size(µm×µm) 20.8×20.8 14.8×14.8 10.7×10.7 8.7×8.7 5.9×5.9 NDPW@0.2DD 9 68 175 450 1820 One Wafer Boat(25) 225 1700 4375 11250 45500 Dies per wafer(×106) 41 143 274 415 2030

Figure 13. The Wafer Size, Technology used and Gates realized.

In Table 5 for calculating the number of dies per wafer we use the following equation taken from connexions module m33385, Part-9_Journey of IC Technology:

– (

Figure 14. Sectoral Composition of $173.6b sales estimate by Altera in 2003 in terms of Consumption. Figure 15. Sectoral Composition of$173.6b sales estimate by Altera in 2003 in terms of Function.

As shown in Figure 16 , Programmable Array Logic (PAL) is formed from a programmable AND and fixed OR array.

Figure 16. Programmable Array Logic (PAL) formed from programmable AND Array and fixed OR Array.

We see in Figure 16 all intersections on decoder side that is on AND array side are shorted. By applying 10V Voltage pulse as we did in EEPROM, the NMOS can be disabled. The rest shorts are retained. Since here we have full options for removing the shorts we say that AND Array is programmable.

On the encoder side we have no such option. Some intersections are shorted and remaining are kept open. Here the OR Array is fixed. User has no options.

In Figure 17, we have Programmable Logic Arrays.

Figure 17. Programmable Logic Array. Both AND array and OR array are programmable.

As seen in the figure, on decoder as well as encoder side all intersections are shorted. User can remove the short on the AND array side(decoder side) as well as on OR array side(encoder side) according to his Boolean function requirement. Hence we say that AND array is programmable as well as OR array is programmable.

This PLA became the basis of SPLD, CPLD and FPGA.

References: “ Microelectronics” by Millman & Grabel, McGraw Hill, 1988.

“Principles of Digital Systems Design using VHDL”, by Roth and John, CENGAGE Learning, 1998.

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