DSD_Chapter 6_Mighty Spartans in Action_Introduction.

Spartan2 and Spartan3 is the name assigned to FPGA developed by the company Xilinx. This name has come from the name Sparta of a City State in Greece in 1000BC. At that time there were two City States Sparta and Athens. Sparta had Oligarchy form of government whereas Athens had Democratic form of government.

Sparta was unique in the ancient times for its social system and constitution, which completely focused on military training and excellence and it dominated Greece peninsula up to 300BC. Subsequently by 100BC it was conquered by Romans. Its inhabitants were classified as Spartan citizens, who enjoyed full rights, non-Spartan free men raised as Spartans, freedmen and state-owned serfs (enslaved non-Spartan local population). Spartans underwent rigorous military training and education regimen, and Spartan soldiers were widely considered to be among the best in battle. Spartan women enjoyed considerably more rights and equality to men than elsewhere in the classical world. Spartans remained a city state which fascinated the people of all cultures and of all times. Thus we have FPGA named Spartan2 and Spartna3.

The following excerpts have been taken from EE Times:

“Since their introduction in the mid-80s, FPGAs have managed to wedge themselves as a fixture into the electronics design landscape. Sitting somewhere between off-the-shelf (OTS) logic, ASICs, OTS processors, and ASSPs, they continue to enjoy growth predictions beyond those of the rest of the semiconductor industry”.

An application specific standard product or ASSP is an Integrated Circuit that implements a specific function that appeals to a wide market. As opposed to ASIC that combines a collection of functions and designed by or for one customer, ASSPs are available as off-the-shelf components. ASSPs are used in all industries, from automotive to communications.

Examples of ASSPs are integrated circuits that perform video and/or audio encoding and/or decoding.

“The latest high-end devices: 28 nm silicon, more metallization layers than ever before, and equivalent gate counts that would see any self-respecting ASIC proud. Historically, these leading edge devices have found the greatest use in networking, DSP, and military/aerospace applications. These are domains where raw performance requirements exceed those available from software-only solutions, but whose volumes cannot always justify the costs of custom silicon development. These devices are more than capable of hosting a full 32-bit soft processor core running at around 50 to 100 MHz as well as several soft peripherals such as a video display driver, UART, Ethernet controller, or IDE controller”.

“Field-programmable gate arrays (FPGAs) have become incredibly capable with respect to handling large amounts of logic, memory, digital-signal-processor (DSP), fast I/O, and a plethora of other intellectual property (IP)”.“At 28-nm, FPGAs deliver the equivalent of a 20- to 30-million gate application-specific integrated circuit (ASIC). At this size, FPGA design tools, which have traditionally been used by just one or two engineers on a project, begin to break down. It is no longer practical for a single engineer, or even a very small design team, to design and verify these devices in a reasonable amount of time”.“Due to recent technological developments, high-performance floating-point signal processing can, for the first time, be easily achieved using FPGAs. To date, virtually all FPGA-based signal processing has been implemented using fixed-point operations. This white paper describes how floating-point technology on FPGAs is not only practical now, but that processing rates of one trillion floating-point operations per second (teraFLOPS) are feasible—and on a single FPGA die. Medical imaging equipment is taking on an increasingly critical role in healthcare as the industry strives to lower patient costs and achieve earlier disease prediction using noninvasive means. To provide the functionality needed to meet these industry goals, equipment developers are turning to programmable logic devices such as Altera's FPGAs”.

“Consumer applications ranging from cell phones, computers, TVs and even digital picture frames are incorporating wireless communication transceivers to implement broadband standards such as LTE(long term evolution), WiMAX and WiFi to provide wireless connectivity to the outside world. These transceivers rely on an analog interface in the digital baseband processor System-on-Chip (SoC) to connect with the RF block. This analog interface is constantly evolving to adapt to the different communications standards”.

We are going to use Spartan2 to implement Digital Systems desined using VHDL.

6.1. Design of BCD –to-Seven Segment Decoder-Driver.

This is available as a MSI_IC chip by the TTL code name 7447. This converts a binary code into its equivalent decimal magnitude and drives a Seven-Segment LED Display to display the corresponding decimal magnitude. We will give the behavioral architecture description and implement it on Spartan2.

VHDL codes of BCD-to-Seven Segment Decoder is the following:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity BCD_to_Seven is

__Port ( bcd : in STD_LOGIC_VECTOR(3 downto 0);

______ seven : out STD_LOGIC_VECTOR(7 downto 1));

end BCD_to_Seven;

architecture Behavioral of BCD_to_Seven is

begin

_________process(bcd)

_______________begin

____________________case bcd is

________________________when"0000"=>seven<="0111111";

________________________when"0001"=>seven<="0000110";

________________________when"0010"=>seven<="1011011";

________________________when"0011"=>seven<="1001111";

________________________when"0100"=>seven<="1100110";

________________________when"0101"=>seven<="1101101";

________________________when"0110"=>seven<="1111101";

________________________when"0111"=>seven<="0000111";

________________________when"1000"=>seven<="1111111";

________________________when"1001"=>seven<="1101111";

________________________when others=> null;

____________________end case;

_________end process;

end Behavioral;

On clicking “View Technology Schematic” we get:

Expanded RTL Schematic:

Expanded Technology Schematic gives:

Now we create the test bench and validate its functionality.

Since this is not a FSM (finite state machine), we need not define the Clock.

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

USE ieee.std_logic_unsigned.all;

USE ieee.numeric_std.ALL;

ENTITY Tb_BCD_to_Seven IS

END Tb_BCD_to_Seven;

ARCHITECTURE behavior OF Tb_BCD_to_Seven IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT BCD_to_Seven

PORT(

bcd : IN std_logic_vector(3 downto 0);

seven : OUT std_logic_vector(7 downto 1)

);

END COMPONENT;

--Inputs

signal bcd : std_logic_vector(3 downto 0) := (others => '0');

--Outputs

signal seven : std_logic_vector(7 downto 1);

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: BCD_to_Seven PORT MAP (

bcd => bcd,

seven => seven

);

-- Stimulus process

stim_proc: process

begin

-- hold reset state for 10 ns.

-- insert stimulus here

bcd<="0000";

wait for 10 ns;

bcd<="0001";

wait for 10 ns;

bcd<="0010";

wait for 10 ns;

bcd<="0011";

wait for 10 ns;

bcd<="0100";

wait for 10 ns;

bcd<="0101";

wait for 10 ns;

bcd<="0110";

wait for 10 ns;

bcd<="0111";

wait for 10 ns;

bcd<="1000";

wait for 10 ns;

bcd<="1001";

wait for 10 ns;

wait;

end process;

END;

The output of the simulation is as follows:

As we can see in the above graphical figure, corresponding to binary code “0000” we have the output “0111111”. That is a,b,c,d,e,f LEDs are lit up and g is OFF. Hence we get a figure:

This Seven-Segment Display is an integral part of Digital Meters, Digital Clocks and Digital Instruments. The Seven-Segment Display with the BCD-to-Seven Segment Decoder and N-Modulus Decade Counter is the basic sub-system of Digital Clocks. This will be taken up later on in the chapter while designing hour-minute-second clock.

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This work is licensed by Bijay_Kumar Sharma under a Creative Commons Attribution License (CC-BY 3.0), and is an Open Educational Resource.

Last edited by Bijay_Kumar Sharma on Oct 25, 2010 6:44 am -0500.