Below is the structure of a line of assembly code.

Labels identify a line of code or a variable and represent a memory address that contains either an instruction or data. The first character of a label must be must be in the first column and must be a letter or an underscore (_) followed by a letter. Labels can include up to 32 alphanumeric characters.

An instruction that executes in parallel with the previous instruction signifies this with parallel bars (||). This field is left blank for an instruction that does not execute in parallel with the previous instruction.

Every instruction in the C6x can execute conditionally. There are five registers available for conditions (on the C67x processors): A1, A2, B0, B1, and B2. If blank, the instruction always executes. Conditions can take a form such as [A1] where the instruction will execute if A1 is not zero. This can be handy for making loops were the counter is put in a register like A1 and is counted down to zero. The condition is put on the branch instruction that branches back to the beginning of the loop.

Where are the numbers stored in the CPU? In the C6000, the numbers used in operations are stored in register. Because the registers are directly accessible though the data path of the CPU, accessing the registers is much faster than accessing data in the external memory.

The C6000 CPU has two register files (A and B). Each of these files consists of sixteen 32-bit registers (A0-A15 for file A and B0-B15 for file B). The general-purpose registers can be used for data, data address pointers, or condition registers. The following figure shows a block diagram of the C67x processors. This basic structure is similar to other processors in the C6000 family.

Figure 1: TMS320C67x DSP Block Diagram taken from SPRU733: TMS320C67x/C67x+ DSP CPU and Instruction Set Reference Guide

The general-purpose register files support data ranging in size from 16-bit data through 40-bit fixed-point. Values larger than 32 bits, such as 40-bit long quantities, are stored in register pairs. In a register pair, the 32 LSB's of data are placed in an even-numbered register and the remaining 8 MSB's in the next upper register (which is always an odd-numbered register). In assembly language syntax, a colon between two register names denotes the register pairs, and the odd-numbered register is specified first. For example, A1:A0 represents the register pair consisting of A0 and A1.

Let's for now focus on file A only. The registers in the register file A are named A0 to A15. Each register can store a 32-bit binary number. Then numbers such as a, x, prod and y above are stored in these registers. For example, register A0 stores a. For now, let's assume we interpret all 32-bit numbers stored in registers as unsigned integer. Therefore the range of values we can represent is 0 to 232232 size 12{2 rSup { size 8{"32"} } } {}−1. Let's assume the numbers a, x, prod and y are in the registers A0, A1, A3, A4, respectively. Then the above assembly instructions can be written specifically:

MPY .M1 A0,A1,A3
    ADD .L1 A4,A3,A4
    

The TI C6000 CPU has a load/store architecture. This means that all the numbers must be stored in the registers before being used as operands of the operations for instructions such as MPY and ADD. The numbers can be read from a memory location to a register (using, for example, LDW, LDB instructions) or a register can be loaded with a constant value. The content of a register can be stored to a memory location (using, for example, STW, STB instructions).

In addition to the general-purpose register files, the CPU has a separate register file for the control registers. The control registers are used to control various CPU functions such as addressing mode, interrupts, etc.

Where do the actual operations such as multiplication and addition take place? The C6000 CPU has several functional units that perform the actual operations. Each register file has 4 functional units named .M, .L, .S, and .D. The 4 functional units connected to the register file A are named .M1, .L1, .S1, and .D1. Those connected to the register file B are named .M2, .L2, .S2, and .D2. For example, the functional unit .M1 performs multiplication on the operands that are in register file A. When the CPU executes the MPY .M1 A0, A1, A3 above, the functional unit .M1 takes the value stored in A0 and A1, multiply them together and stores the result to A3. The .M1 in MPY .M1 A0, A1, A3 indicates that this operation is performed in the .M1 unit. The .M1 unit has a 16 bit multiplier and all the multiplications are performed by the .M1 (or .M2) unit. The following diagram shows the basic architecture of the C6000 family and functional units.

Figure 2: Functional Units of the 'C6x taken from SPRU198: TMS320C6000 Programmers' Guide

Similarly, the ADD operation can be executed by the .L1 unit. The .L1 can perform all the logical operations such as bitwise AND operation (AND instruction) as well as basic addition (ADD instruction) and subtraction (SUB instruction).

Quite often you need to load a register with a constant. The C6x instructions you can use for this task are MVK, MVKL, and MVKH. Each of these instructions can load a 16-bit constant to a register. The MVKL instruction loads the LOWER 16-bits and the MVKH instruction loads the HIGH 16-bits into the register. In order to load 32-bit values into a register, both instructions are needed.

Contents of one register can be copied to another register by using the MV instruction. There is also the ZERO instruction to set a register to zero.

Because the C6x processor has the so-called load/store architecture, you must first load up the content of memory to a register to be able to manipulate it. The basic assembly instructions you use for loading are LDB, LDH, and LDW for loading up 8-, 16-, and 32-bit data from memory. (There are some variations to these instructions for different handling of the signs of the loaded values.)

However, to specify the address of the memory location to load from, you need to load up another register (used as an address index) and you can use various addressing modes to specify the memory locations in many different ways. The addressing mode is the method by which an instruction calculates the location of an object in memory. The table below lists all the possible different ways to handle the address pointers in the C6x CPU. Note the similarity with the C pointer manipulation.

The [disp] specifies the number of elements in word, halfword, or byte, depending on the instruction type and it can be either 5-bit constant or a register. The increment/decrement of the index registers are also in terms of the number of bytes in word, halfword or byte. The addressing modes with displacements are useful when a block of memory locations is accessed. Those with automatic increment/decrement are useful when a block is accessed consecutively to implement a buffer, for example, to store signal samples to implement a digital filter.

Loc   32-bit value
100h  fe54  7834h
104h  3459  f34dh
108h  2ef5  7ee4h
10ch  2345  6789h
110h  ffff  eeddh
114h  3456  787eh
118h  3f4d  7ab3h
	    

Storing the register contents uses the same addressing modes. The assembly instructions used for storing are STB, STH, and STW.

Sometimes, it becomes necessary to access part of the data stored in memory. For example, if you store the 32-bit word 0x11223344 at memory location 0x8000, the four bytes having addresses location 0x8000, location 0x8001, location 0x8002, and location 0x8003 contain the value 0x11223344. Then, if I read the byte data at memory location 0x8000, what would be the byte value to be read?

The answer depends on the endian mode of the memory system. In the little endian mode, the lower memory addresses contain the LSB part of the data. Thus, the bytes stored in the four byte addresses will be as shown in Table 3.

In the big endian mode, the lower memory addresses contain the MSB part of the data. Thus, we have

In the C6x CPU, it takes exactly one CPU clock cycle to execute each instruction. However, the instructions such as LDW need to access the slow external memory and the results of the load are not available immediately at the end of the execution. This delay of the execution results is called delay slots.

	   1     LDW   .D1    *A10, A1
	   2     MV    .D1    A1,A2
	  

	    1     LDW    .D1    *A10, A1
	    2     NOP
	    3     NOP
	    4     NOP
	    5     NOP
	    6     MV     .D1    A1,A2
	  

	    1     LDW    .D1    *A10, A1
	    2     NOP  4
	    3     MV     .D1    A1,A2
	  

Then, why didn't the designer of the CPU make such that LDW instruction takes 5 clock cycles to begin with, rather than let the programmer insert 4 NOPs? The answer is that you can insert other instructions other than NOPs as far as those instructions do not use the result of the LDW instruction above. By doing this, the CPU can execute additional instructions while waiting for the result of the LDW instruction to be valid, greatly reducing the total execution time of the entire program.

In the C6x CPU, it takes exactly one CPU clock cycle to execute each instruction. However, the instructions such as LDW need to access the slow external memory and the results of the load are not available immediately at the end of the execution. This delay of the execution results is called delay slots.

	   1     LDW   .D1    *A10, A1
	   2     MV    .D1    A1,A2
	  

	    1     LDW    .D1    *A10, A1
	    2     NOP
	    3     NOP
	    4     NOP
	    5     NOP
	    6     MV     .D1    A1,A2
	  

	    1     LDW    .D1    *A10, A1
	    2     NOP  4
	    3     MV     .D1    A1,A2
	  

Why didn't the designer of the CPU make such that LDW instruction takes 5 clock cycles to begin with, rather than let the programmer insert 4 NOPs? The answer is that you can insert other instructions other than NOPs as far as those instructions do not use the result of the LDW instruction above. By doing this, the CPU can execute additional instructions while waiting for the result of the LDW instruction to be valid, greatly reducing the total execution time of the entire program.

The functional unit latency indicates how many clock cycles each instruction actually uses a functional unit. All C6x instructions have 1 functional unit latency, meaning that each functional unit is ready to execute the next instruction after 1 clock cycle regardless of the delay slots of the instructions. Therefore, the following instructions are valid:

	1     LDW    .D1    *A10, A4
	2     ADD    .D1    A1,A2,A3
	

Although the first LDW instruction do not load the A4 register correctly while the ADD is executed, the D1 functional unit becomes available in the clock cycle right after the one in which LDW is executed.

To clarify the execution of instructions with delay slots, let's think of the following example of the LDW instruction. Let's assume A10 = 0x0100A2=1, and your intent is loading A9 with the 32-bit word at the address 0x0104. The 3 MV instructions are not related to the LDW instruction. They do something else.

	  1     LDW    .D1    *A10++[A2], A9
	  2     MV     .L1    A10, A8
	  3     MV     .L1    A1, A10
	  4     MV     .L1    A1, A2
	  5     ...
	

We can ask several interesting questions at this point:

Similar theory holds for MPY and B (when using a register as a branch address) instructions. The MPY reads in the source values in the first clock cycle and loads the multiplication result after the 2nd clock cycle. For B, the address pointer is read in the first clock cycle, and the actual branching occurs after the 5th clock cycle. Thus, after the first clock cycle, you are free to modify the source or the address pointer registers. For more details, refer Table 3-5 in the instruction set description or read the description of the individual instruction.

There are several instructions for addition, subtraction and multiplication on the C6x CPU. The basic instructions are ADD, SUB, and MPY. ADD and SUB have 0 delay slots (meaning the results of the operation are immediately available), but the MPY has 1 delay slot (the result of the multiplication is valid after an additional 1 clock cycle).

Often you need to control the flow of the program execution by branching to another block of code. The B instruction does the job in the C6x CPU. The address of the branch can be specified either by displacement or stored in a register to be used by the B instruction. The B instruction has 5 delay slots, meaning that the actual branch occurs in the 5th clock cycle after the instruction is executed.

In many cases, depending on the result of previous operations, you execute the branch instruction conditionally. For example, to implement a loop, you decrement the loop counter by 1 each time you run a set of instructions and whenever the loop counter is not zero, you need to branch to the beginning of the code block to iterate the loop operations. In the C6x CPU, this conditional branching is implemented using the conditional operations. Although B may be the instruction implemented using conditional operations most often, all instructions in C6x can be conditional.

Conditional instructions are represented in code by using square brackets, [ ], surrounding the condition register name. For example, the following B instruction is executed only if B0 is nonzero:

	  1    [B0]    B     .L1    A0
	

To execute an instruction conditionally when the condition register is zero, we use ! in front of the register. For example, the B instruction is executed when B0 is zero.

	  1    [!B0]    B     .L1    A0
	

Not all registers can be used as the condition registers. In the C62x and C67x devices, the registers that can be tested in conditional operations are B0, B1, B2, A1, A2.

The logical operations and bit manipulations are accomplished by the AND, OR, XOR, CLR, SET, SHL, and SHR instructions.

Other useful instructions include IDLE and compare instructions such as CMPEQetc.

The set of instructions that can be performed in each functional unit is as follows (See Table 6, Table 7, Table 8 and Table 9). Please refer to TMS320C62x/C67x CPU and Instruction Set Reference Guide for detailed description of each instruction.

Then, what are the constraints on the parallel instructions? Let's look at the resource constraints in more detail.

	    1          ADD     .L1x    A0,B1,A2
	    2   ||     MPY     .M1x    A5,B0,A3
	  

	    1          LDW     .D2     *B0, A1
	  

	    1          LDW     .D1     *A0, A1
	    2   ||     STW     .D2     A2, *B0
	  

	    1          ADD     .L1     A1, A1, A2
	    2   ||     MPY     .M1     A1, A1, A3
	    3   ||     SUB     .D1     A1, A4, A5
	  

	    1	       ADD     .L1     A1, A1, A2
	    2   ||     MPY     .M1     A1, A1, A2
	  

	    1          MPY     .M1     A1, A1, A2
	    2          ADD     .L1     A3, A4, A2