SSPD_Chapter 6_Part 8_Caliberating ATHENA for typical MOSFET FLOW

7.8 Caliberating ATHENA for typical MOSFET FLOW.

This section of the manual provides information on which parameters should be tuned in the input file to provide predictive simulations using a typical MOSFET process flow. We assume you are now familiar with the mechanics of making an input file and using the correct methods and models (see Section 7.7.3:“Choosing Models In SSUPREM4”). For example, incorrect use of the METHOD statement will invalidate the rest of the following section.

Calibrating an ATHENA input file for a typical MOS process flow involves using the device simulator, ATLAS, since electrical measurements from the MOSFETs in question often represents the majority of the physical data available for calibration. This can be thought as a paradox since ATLAS would also have to be correctly calibrated. The reason that this doesn’t present a problem is discussed below.

An important point to remember when using Technology Computer Aided Design (TCAD) is that the most critical task is to accurately model the process flow.

Note: For accurate MOSFET simulation, you should invest 90%of the time in achieving an accurate process simulation, while only investing 10%of the time in fine-tuning the device simulation.

The reason for this, especially for silicon technologies, is that the device physics, in general, is understood. For silicon, not only is the physics well understood, it is also well characterized, so most of the default values in ATLAS will be correct. Therefore, the calibration of an ATHENA process file does not involve the calibration of well known quantities such as diffusion coefficients. Instead, the calibration involves variables that are process and production line dependent. For example, the damage caused by an implant cannot be determined exactly, since it is dose rate dependent and can be influenced by beam heating of the substrate, which is dependent on the carousel rotation speed and the efficiency of the cooling system.

Note: If the process has been correctly modeled, the device simulation will also be accurate if appropriate models have been chosen.

If a simulated device exhibits electrical characteristics that are totally inaccurate, you may have done something wrong in the process simulation. Do not make the mistake of changing well known default values in the simulators to make a curve fit one set of results because this will lead to poor predictive behavior. Try and find the cause of a discrepancy.

7.8.1: Input Information

It may seem obvious but must be emphasized that an accurate process flow is vital for simulation accuracy, especially for Rapid Thermal Anneals (see Section 7.7.8:“Simulating Rapid Thermal Anneals (RTA) Notes” for details). Other process information required is an accurate cross-section of the oxide spacer. Modeling the spacer profile accurately ensures the lateral damage distribution due to the subsequent source-drain implants is correctly modeled.

Turning to electrical data, the most important device electrical data is a plot of threshold voltage versus gate length for the NMOS devices. Figure 7.40 shows typical plots of threshold voltage versus gate length. In this figure, the RTA anneal temperature and times were varied to show the various profiles that can be expected. A more typical plot is represented by the 1000°C RTA profile, showing a peak value around 1-2 microns with a tail off for longer or shorter gate lengths.

Figure 7.40: A plot of Threshold Voltage vs. Gate Length for NMOS devices(given in next module)

Gate oxide thickness measurements are also required. Be careful here if oxide thickness is measured with capacitance-voltage (C-V) methods, since quantum effects in very thin oxides (less than 5nm) can lead to inaccuracies because the actual location of the peak concentration of the accumulation charge is not at the interface as classic physics predicts but a short distance into the silicon. Use the QUANTUM model in ATLAS to match accumulation capacitance with oxide thickness for very thin oxides.

Other useful electrical input information is data that won’t be used now but later for the calibration process itself, testing the predictive nature of the simulation. Typical device characteristics used for predictive testing includes threshold voltage versus gate length measurements for a non-zero substrate bias.

7.8.2: Tuning Oxidation Parameters

During oxidation, interstitials are injected into the silicon substrate by the advancing interface. The first parameter to tune is the fraction of consumed silicon atoms that are re-injected back into the substrate as interstitials. In ATHENA, the related tuning parameter is called THETA.0 and is defined in the INTERSTITIAL statement. THETA.0 has been found to be slightly different for wet and dry oxides. The default value is reasonably accurate for dry oxides but some tuning may be required for wet oxidation.

The major effect of interstitial injection during gate oxidation is to create enhanced diffusion of the threshold adjust implant. The measured threshold voltage of the final device is very sensitive to the dopant concentration near the silicon-gate oxide interface. Consequently, threshold voltage measurements are a sensitive indicator of interstitial behavior. Oxidation, however, is not the only source of interstitial injection. The source-drain and LDD implants also induce a large concentration of interstitials. In order to isolate oxidation enhanced diffusion, the threshold voltage of a long gate length device is used, preferably where L=20 µm or more, so that the threshold voltage will be little influenced by damage near the source-drain regions.

Interstitials injected by source-drain implant damage can travel up to 10 µm along the surface before recombination takes place. A gate length of 20 µm is recommended as the minimum gate length for calibration so this can allow the interstitials to diffuse 10 µm along the surface from both the source and drain ends without effecting diffusion near the center of the device. In summary, tuning THETA.0 involves the comparison of modeled and measured threshold voltage data for a long gate-length device.

THETA.0 can be rapidly tuned by taking a one dimensional (1D) vertical cutline through the center of the gate and doing a 1D process simulation. You can either tune THETA.0 manually or by using the Optimize function in DECKBUILD. Theta.0 is tuned until the measured and simulated data of the long channel threshold voltage correspond. The fine tuning of THETA.0 is performed by using a full 2D simulation.

Figure 7.41 shows a typical dependence of extracted threshold voltage on the Theta.0 tuning parameter. Realistic values of THETA.0 correspond to the rising part of the curve. The glitch in the curve is due to rounding errors in the EXTRACT statement used to calculate the threshold voltage due to the automatic and independent mesh generated in the EXTRACT statement. The mesh can be changed from its default value shown here to eliminate this effect. But close examination reveals that the error is only a few millivolts off, which is accurate enough for most process parameter extractions.

Figure 7.41: A Typical Dependence of Extracted Threshold Voltage on Theta.0

X-axis = Theta.0, Y-axis = Threshold Voltage.

7.8.3: Tuning Implantation Parameters

You can now tune two implantation parameters by using the threshold voltage versus gate length data. The peak value of threshold voltage for a given process flow (the reverse short channel effect) will be a function of the initial implant damage caused by the LDD and source-drain implants. Since these implants have a high total dose and damage, the tuning parameter here is the clustering factor. In ATHENA, this parameter is called CLUST.FACT and is defined in the CLUSTER statement. The higher the clustering factor, the greater the damage, and the greater the diffusion, the greater the reverse short channel effect.

Figure 7.42 shows the effect on the threshold voltage of changing the CLUST.FACT parameter for a typical process flow.

Figure 7.42: How Changing the clust.fact parameter affects the threshold voltage

The second implantation parameter that can now be tuned is the lateral spread of the implant near the surface. In ATHENA, this parameter is called LAT.RATIO1 and is defined in the IMPLANT statement. The lateral spread of the source-drain and LDD dopant is responsible for the classical short channel effect, where the threshold voltage reduces for very short channel lengths. Simply tune the LAT.RATIO1 parameter until the onset of classical short channel effects of simulated and measured data correspond. If the LAT.RATIO1 is increased, the onset of the classical short channel effect will occur for longer gate lengths.

7.8.4: Tuning Diffusion Parameters

The final part of the threshold voltage versus gate length curve can now be used to tune the surface recombination rate of interstitials. In ATHENA, this parameter is called KSURF.0 and is specified in the INTERSTITIAL statement. The surface recombination of interstitials will dictate the roll-off rate of threshold voltage from its peak value (reverse short channel effect) to the long gate length value. Once again, simply tune KSURF.0 until the long channel threshold voltage roll off rate matches that of the measured data.

PMOS Tuning

PMOS devices are a special case since the boron doped Source/Drain implants overall tend to absorb interstitials rather than emit them. The reverse short channel effect in buried channel PMOS devices can be caused by high angle implants. If high angle implants are used, the reverse short channel effect can be tuned using the LAT.RATIO1 parameter in the IMPLANT statement.

7.8.5: Related Issues on using the Device Simulator ATLAS for MOS Process Tuning

It should now be known that calibrating an ATHENA process file involves using the device simulator ATLAS to a significant extent. Hence, it’s imperative that the use of the device simulator doesn’t create additional errors, rendering the process calibration results invalid.

Fortunately, the device physics involved in simulating the conditions required to extract a threshold voltage are not demanding. The drain voltage required to extract a threshold voltage is only 50-100mV so effects such as impact ionization can be neglected. The field perpendicular to the gate is also relatively low around the threshold voltage so field effects in this direction will do little effect. We recommend, however, using at least the models SRH and CVT during the calculation. Other parameters for silicon are sufficiently well known for silicon to the point that the results from the device simulator are reliable.

The first important point is to ensure that you let the device simulator calculate the work function of the gate electrode from the simulated doping profile rather than assigning a value to it. This means, making sure that the polysilicon gate is not itself defined as an electrode but rather a layer of metal, usually aluminum, is deposited on top of the polysilicon gate. Therefore, this metal layer is the film defined as the electrode. Do not assign a work function to this deposited metal electrode to ensure that it behaves as an ohmic contact rather than a Schottky contact. The effective work function of the poly gate will then be correctly calculated from the doping profile in the polysilicon.

An important area for accuracy in MOSFETs is modeling the inversion region under the gate. As it is, this charge that is responsible for current conduction in the device. The inversion region charge under the gate-only extends approximately 30 Angstroms into the silicon. The inversion region charge density under the gate falls off rapidly with depth into the silicon. It is imperative that there are several mesh points in the Y direction in this inversion region to model the drain current correctly. Accordingly, we recommend that the mesh spacing under the gate be no more than 10 Angstroms (1 nm).

You would think that a 10 Angstrom mesh under the gate would result in a huge number of mesh points. But, there only needs to be approximately three mesh points within the inversion region in the Y direction. The grid spacing can increase rapidly in spacing away from the oxide-silicon interface.

Figure 7.43 shows the effects of changing the mesh spacing at the interface on the simulated drain current. You can see from this figure that too coarse of a mesh always results in too high of a current simulated.

Figure 7.43: The effect of changing the mesh spacing at the interface on the simulated drain current

If contact resistance is a problem, then include it in the CONTACT statement. The resistance added to the CONTACT statement should be the measured resistance per contact divided by the number of contacts on each individual electrode. Obviously for D.C. measurements, the resistance on the gate contact will have no effect on the results since no current flows in this direction.

Checking the Predictive Powers of Tuned Process Parameters

If the process simulation has been correctly tuned, the process and device simulators should have predictive powers. To check the validity of the tuning process, use a new set of electrical data that was not used during the tuning process. For example, a good alternative set of data is to check the threshold voltage versus gate length for a non-zero voltage applied to the MOSFET body contact.

Conclusion

Using just one set of easily obtained measured electrical data, namely a plot of threshold voltage versus gate length, you can obtain most of the tuning parameters required for accurate process simulation. The other most important piece of data required is an accurate measurement of the gate oxide thickness, which is routinely measured in any instance.

You have been given specific advice as to which process and device models to use for each process in order to get the best results out of the simulation software. In particular, the correct use of models for the implantation and diffusion processes is stressed, as this has a dramatic effect on MOSFET characteristics, especially as anneal times and device dimensions decrease.

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This work is licensed by Bijay_Kumar Sharma under a Creative Commons Attribution License (CC-BY 3.0), and is an Open Educational Resource.

Last edited by Bijay_Kumar Sharma on Apr 6, 2011 11:21 pm -0500.