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SSPD_Chapter 6_Part 9_Appendix Device Physics

Module by: Bijay_Kumar Sharma. E-mail the author

Summary: SSPD_Chapter 6_Part 9_Appendix on Device Physics describes the models used in ATLAS and ATHENA

SSPD_Chapter 6_Part 9_Appendix Device Physics

Section I. The Bipolar Junction Transistor Technology in 60’s-70’s.

In 1959 at the time IC Technology was invented, the vertical NPN transistor looked as given in Figure I.

Figure 1
Figure 1 (Picture 2.png)

Figure I. Cross-sectional view and Plan view of Vertical NPN transistor.

(25um by 37.5um base stripe geometry)

Total area covered 212 μm by 250 μm

Substrate is 100um thick.

Epitaxial layer is 10um thick.

Base Collector Junction is at 3um depth and Emitter-Base Jn. at 2um depth.

Hence Base Width = WB = 1 um thick.

P Substrate- ρ=10 Ω-cm, NA= 1015 Boron atoms/cc;

Buried Layer has been put to reduce Collector Series Resistance.

ND=1019Arsenic Atoms/cc; In buried layer Arsenic is used as donor type dopent because it has much lower diffusion coefficient hence almost negligible out diffusion in subsequent diffusion and heating cycles.

N Epitaxial layer- ρ= 0.1 Ω-cm, ND= 1016 Phosphorous Atoms/cc;

Base layer- NA= 1017 Boron Atoms/cc; Base layer has a sheet resistance of 200 Ω/sq.

Emitter and Collector Contact layer- ND= 1019 Phosphorous Atoms/cc, Rsh = 1Ω/sq;

Section II. The Bipolar Junction Transistor Technology in 1980’s-2000’s.

Gordon Moore is a co-founder of Intel and he made an empirical observation which became a Law . It stated :

“ at our rate of technological development, the complexity of an integrated circuit, with respect to minimum component cost will double in about 24 months”.[“Cramming more components onto Integrated Circuits”, Electronics Magazine,19 April 1965]. The law has held the test of time to date as is evident from Table I.4_50 years journey of IC Technology_Appenidix I.

Today Moore’s Law has become a self fulfilling prophecy and a goal Industry tries to achieve all the time. In attempting to maintain this rate of growth, enormous R&D has gone into the development of tools and equipments required for IC fabrication and into the advancement of processing techniques required for IC fabrication.

Section III.1. The relation between the physical parameters and performance parameters and Physics of High Performance nano BJT.


Figure 2
Figure 2 (graphics1.png)

Here αF = γ×β*

= (Emitter Injection Efficiency) × (Base Transport Factor)

Current Transfer Ratio

Figure 3
Figure 3 (graphics2.png)

In Eq. I , M = Avalanche Multiplication Factor =

Figure 4
Figure 4 (graphics3.png)

Where n is Miller Indices ranging from 2 to 7.

At normal Collector to Base Voltages, M = 1

But as VCB becomes large approaching BVCBO , M becomes a very large number and eventually it becomes infinite at VCB = BVCBO . This is known as CB Junction Breakdown by Avalanche mechanism.

At low doping we have to invoke Impact Ionization Model or Avalanche Mechanism. At doping densities larger than 1018 dopent /cc we must invoke mechanism of tunnelling also known as Zener Breakdown Model.

As seen in Figure II, area enclosed by Forward Active Mode bracket is the Forward Active Mode region of operation of CB BJT. In this region the active device behaves as a linear device and is suitable for linear applications. The safe operating voltage range extends from 0 V to (BVCBO – 2 V) in CB BJT.

Figure 5
Figure 5 (Picture 3.png)

In CE BJT, Equation I is rearranged as shown below:

Figure 6
Figure 6 (graphics4.png)

At low voltages, Equation II reduces to :

Figure 7
Figure 7 (graphics5.png)

This further simplifies to:

Figure 8
Figure 8 (graphics6.png)


Figure 9
Figure 9 (graphics7.png)

Here ICBO= Collector Current in CB BJT with Emitter Open that is Emitter current is held at zero magnitude. This current is the reverse leakage current across the reverse biased CB Junction and is of the order of nA.

Here ICEO= Collector Current in CE BJT with Base Open that is Base current is held constant. This current is not the reverse leakage current across the reverse biased CB Junction. It is the Collector Current with BJT in Forward Active Mode and it is of the order of µA.

Equation IV indicates that at a given ‘VCE*’ αFM becomes UNITY and both the terms in the Equation become infinity. Physically this means that as VCE increases, by Base Width Modulation also known as Early Effect, forward current transfer ratio improves. Simultaneously M is also gradually increasing as seen in Equation III. Hence Collector to Emitter Breakover takes place across Collector to Emitter terminals and this voltage is designated as BVCEO .


Figure 10
Figure 10 (graphics8.png)

Rearranging the terms we get:

Figure 11
Figure 11 (graphics9.png)

Therefore if Collector-Base Breakdown occurs at 128 V then Collector-Emitter Breakover with constant base current drive occurs at 60V as shown in Figure III. The range of voltage over which BJT can be safely operated is drastically reduced. The same CE BJT if used with constant voltage drive, as it is in Current Mirror configuration, will experience breakover at 112V.

The physics of this Breakover Phenomena becomes clear from Figure IV and Figure V.

Figure IV shows the electron and hole component of IE , IC and IB at low voltages when reverse leakage current at CB Junction is:

Figure 12
Figure 12 (graphics10.png)

Figure V shows the electron and hole component of IE , IC and IB at high voltages when reverse leakage current at CB Junction is:

Figure 13
Figure 13 (graphics11.png)

Figure 14
Figure 14 (Picture 4.png)

Figure IV and Figure VI must be studied in correspondence. Figure VI shows the carrier concentration profile of NPN transistor in Forward Active Mode.

In Forward Active Mode, EB junction is forward biased and BC junction is reverse biased. Built-in barrier potential at EB is reduced (φBO - VEB) and built-in barrier potential at BC junction is increased (φBO +VCB).

Reduced barrier potential helps in electron(majority carrier) injection into base. In base electron becomes minority carriers hence increased barrier potential at CB junction is down-hill for the minority carriers. Therefore electrons injected into Base transit through the narrow Base region with negligible recombination and are collected by Collector. Since base is narrow practically all the carriers in Base are collected by the Collector.

While electrons are travelling longitudinally across the Vertical NPN BJT they experience recombination in Emitter as well as in Base.

Recombination in Emitter causes Emitter Injection Efficiency (γ) to be less than 100%.

Recombination in Base causes Base Transport Factor (β*) to be less than 100%.

Figure 15
Figure 15 (Picture 5.png)

These two recombinations cause the forward current transfer ratio to be less than UNITY. To provide these two recombinations Base Current is necessitated.

IB = IBB + IEp = provides the holes for recombination in Base + provides the holes to be injected into Emitter and cause hole diffusion current in Emitter.


Figure 16
Figure 16 (graphics12.png)

In Figure VI, charge stored in the Base is shown by the shaded region and is given by the following expression:

Figure 17
Figure 17 (graphics13.png)
Figure 18
Figure 18 (graphics14.png)

Figure 19
Figure 19 (graphics15.png)
Figure 20
Figure 20 (graphics16.png)

In Figure VI, minority carrier densities are depressed near the depletion layer of BC junction. Here EHP are thermally generated since minority carrier density is less than the thermal equilibrium value. The EHP (electron-hole pair) which survive to reach the reverse biased BC junction depletion width are swept across the depletion width as the reverse leakage current. The electrons on Base side and holes on Collector side are swept across the depletion width because the enhanced built-in barrier potential across the BC junction acts as the down-hill for minority carriers on two sides. The electron component of this reverse leakage ICEO adds to the injected electron current being collected by the collector and hole component of the reverse leakage ICEO provide the holes in Base for recombination as shown in Figure IV.

Figure 21
Figure 21 (Picture 6.png)

As VCE increases , down-hill potential gradient becomes very steep which accelerates the minority carriers being swept across the BC junction to the extent that IMPACT IONIZATION and IMPACT GENERATION starts as shown in Figure V. Now a copious amount EHP are generated in reverse biased BC junction. Electrons add to IC increasing it considerably and holes povide recombination centers in Base.

Eventually when αFM becomes UNITY, holes generated by impact ionization provides all the holes required in Base for recombination with injected electrons as well as holes generated by impact ionization provide the holes to be injected into Emitter. Thus requirement for IB from Base terminal becomes zero, current gain becomes infinite and IC shoots up and breakover occurs. At the breakover point S-type negative impedance region is caused as shown in Figure VI. The PHYSICS of BREAKOVER is as follows:

At αFM = 1 the impact generated holes just suffice the recombination needs of the device. At αFM > 1 the impact generated holes are more than what is required for recombination in the Base and for injection into Emitter. Hence the excess part of impact generated holes starts building the concentration of the carriers and their concentration gradient in the Base. This leads to a sudden shoot up in the Collector Current.

The S-type NIR occurs as shown in Figure III, because before breakover αF1 is of the order of 0.7 4 because of very small IC and after the breakover αF2 is of the order of 0.8 because of large IC hence

Figure 22
Figure 22 (graphics17.png)

Figure 23
Figure 23 (graphics18.png)

Rearranging the terms we get:

Figure 24
Figure 24 (graphics19.png)

For 2N2119A: n = 2, BVCBO = 128V, BVCEO = 66 V, αF1 = 0.74; αF2 = 0.8.

Substituting these values we get: VS = 58V.

Section III.2. Band Gap Narrowing in BJT.

In a classical BJT, Emitter Bulk Width(2µm) >> Diffusion Length of minority carriers in Emitter(fraction of a micron). Hence hole (minority carrier in Emitter) diffusion current is non-dominant and d.c. current gain in a classical BJT is :

Figure 25
Figure 25 (graphics20.png)

Figure 26
Figure 26 (graphics21.png)

Figure 27
Figure 27 (graphics22.png)

Therefore in a classical BJT the dc current gain is as given below:

Figure 28
Figure 28 (graphics23.png)
Figure 29
Figure 29 (Picture 7.png)

But as lateral scaling and vertical scaling have scaled down in the process of evolution from SSI to MSI to LSI, base width have been scaled down from 1000nm to 100nm and now they are being scaled down to 10nm. Emitter Bulk Width (WE) have scaled down from 2 microns to a fraction of micron. Hence diffusion length of holes [ LP =√(DPτP) ] in Emitter has become comparable to Emitter Bulk Width and carrier concentration profile is akin to that of a narrow base diode. This means two things:

  1. In the Expression II, Base Recombination Current becomes negligible compared to hole diffusion current in Emitter;
  2. Hole Diffusion current becomes a function of surface recombination velocity at the emitter contact.

At a metal Emitter Contact surface recombination velocity is very high. Hence dc current gain drastically deteriorates.

In Equation XVI , diffusion length is replaced by emitter bulk width and base recombination current is neglected.

Figure 30
Figure 30 (graphics24.png)
Figure 31
Figure 31 (graphics25.png)

Figure 32
Figure 32 (graphics26.png)
Figure 33
Figure 33 (graphics27.png)


Figure 34
Figure 34 (graphics28.png)


Figure 35
Figure 35 (graphics29.png)

If we take the following data:

(ND)E = 1020/cc, (NA)B = 1017/cc, WE = WB = 1µm and DpE=1.25 (cm)2/sec and DnB=20 (cm)2/sec. For homogenous devices we assume Band-gap to be uniform everywhere hence

EgE = EgB = 1.12 eV.

Therefore βF = 1.6×104 ;

As is evident from Equation XVIII, to obtain high gain, Emitter needs to be heavily doped and we need thin Base Region.

Due to heavy doping in Emitter, degeneracy is introduced which leads to Band Gap Narrowing (BGN) by ∆Eg . The radius of the fifth electron or the donor electron orbiting donor atom is 13×10-8cm = 13Angstrom = 13Aº.

Figure 36
Figure 36 (Picture 8.png)

Figure VII. Calculation of critical packing density where donor electrons wave function of donor atoms start to overlap.

Ncrit = 1/Vd= 1/(2rd)3 = 1.7×1019/cc.

When the doping level approaches this critical level, energy level corresponding to donor atoms no more remain DISCRETE but they become a continuum in effect extending the conduction band and narrowing the Forbidden Energy Band Gap which is known as Band Gap Narrowing(BGN). This is a degenerate semiconductor and the Fermi-level lies at the edge of the conduction band or within the conduction band as it is in metal. Hence a degenerate semi-conductor is semi-metal. The energy band diagram of degenerate and non-degenerate semiconductor is given in Figure VIII.

Heavy doping of emitter causes Band Gap Narrowing in Emitter as shown in Figure VIII.

Figure 37
Figure 37 (Picture 9.png)

Figure VIII. The Energy Band Diagram of Pure, doped and heavily doped semiconductor.

There is Band Gap Narrowing in Emitter and Band Gap in Base remains Eg0 therefore we get the following expressions

Figure 38
Figure 38 (graphics30.png)

Figure 39
Figure 39 (graphics31.png)

Figure 40
Figure 40 (graphics32.png)

Substituting Equation XIX in Equation XVIII we get the DC current gain as:

Figure 41
Figure 41 (graphics33.png)


Figure 42
Figure 42 (graphics34.png)

The empirical relationship for BGN is:

Figure 43
Figure 43 (graphics35.png)

Where Eref = 0.009eV and Nref = 1017/cc for typical cases.

Table I. ∆E g vs N D .

Table 1
Emitter Doping DensityND (number per cc) BGN∆Eg (eV)
1020 0.12466
1019 0.083
1018 0.0424
1017 6.36×10-3
1016 1meV

Table II. N Deff vs N D .

Table 2
ND (number per cc) ∆Eg (eV) NDeff (number per cc)
1020 0.12466 8.258×1017
1019 0.083 4×1017
1018 0.0424 1.96×1017
1017 6.36×10-3 8×1016
1016 1meV 1×1016

Heavy doping of emitter causes Band Gap Narrowing in Emitter which limits the improvement in Injection Efficiency due to heavy doping of Emitter. Emitter doping may be ND = 1020/cc but in effect we get the Injection Efficiency corresponding to 1018/cc.

For a doping level of ND = 1020/cc, ∆Eg=0.12eV.

This gives an effective doping level of NDeff = 1018/cc.

If we take into account of BGN, we must use Eq.XX .

Using Eq.XX we get : βF = 160.

Section III.3. Polysilicon emitter BJT (PEBJT)

The carrier concentration profile in CE BJT in forward active mode is shown in Figure VI. In 60s EB junction was like a wide base diode but with dimension scaling and improvement in technology, EB junction became shallow and hence narrow base diode. In a narrow base diode the emitter surface contact is decisive in determining the resultant emitter injection efficiency. As shown in Figure IX, metal contact directly to pure single crystal emitter portion causes a poorer injection efficiency as compared to that where metal contact and n+ pure Silicon has heavily doped poly-Silicon Emitter sandwiched between the two layers.

Table 3

Figure IX. Linear Gradient is a strong function of surface condition. Metal contact gives a large gradient and Poly Silicon contact to Emitter gives a much lower linear gradient on the emitter side thereby improving I Dn /I D (Injection Efficiency) by several orders of magnitude.

To achieve higher degree of integration we had to go for smaller feature size as well as shallow devices. Metallic contact gives infinite surface recombination velocity, hence it gives a much steeper gradient as shown in Fig. IX a. whereas Poly-Silicon gives a much lower gradient resulting in a very low hole component of the total current thereby giving a much higher injection efficiency.

Table III. Room Temperature current gain as a function of emitter contact for device run BIP-8. [“Effect of Emitter Contact on Current Gain of Silicon Bipolar Devices”, T.H.Ning & R.D. Isaac, IEEE Int. Electron Devices Meeting, pp.473-476, 1979].

Table 4
Wafer H H E
Contact Al Pd2Si + Al Poly + Al
RDB (KΩ/▄) 7.2 ± 0.2 7.2 ± 0.2 7.6 ± 1.0
Gain 67 ± 3 51 ± 8 158 ± 12

“ The current gain of silicon bipolar transistors with shallow emitters depends critically on the emitter contact technology…………….The conventional contact by metal or metal silicide degrades the current gain, while contact by a thin layer of poly-silicon is effective in improving the current gain” [ibid].

In Polysilicon emitter BJT (PEBJT), a polycrystalline Si Film lies between Metallic Emitter Contact and Silicon Proper. By ion-implantation, the Polycrystalline Silicon Film is doped with Donor Arsenic Ions. By subsequent annealing, shallow diffusion of Donor Arsenic atoms from N+ Poly-Silicon Source takes place leading to a shallow layer of N+ in Si proper contacted by a similarly doped N+ Poly-Silicon thin film. This structure is known as Polysilicon emitter BJT.

  1. This is suitable for shallow EB Junction;
  2. Compatible with self-aligned processing. This minimizes parasitic Resistance and Capacitances leading to faster response time.
  3. Short Circuit Current Gain (βF) in PET is considerably improved as compared to that of shallow all crystalline emitter of equivalent thickness.

III.3.1. The physics of improvement of Short Circuit Current Gain (β F ) in PET.

Figure 44
Figure 44 (Picture 20.png)

Figure X. Minority Carrier Concentration in a shallow EB Junction case 1. All pure single crystal structure and case 2 in Poly Si Emitter BJT.

Since WE << LpE , therefore there is negligible recombination through out the Emitter. At the interface of Poly Si(region 1) and Pure Si(Region 2), continuity of carrier concentration and continuity of diffusion current requires that:

Figure 45
Figure 45 (graphics36.png)
Figure 46
Figure 46 (graphics37.png)

Figure 47
Figure 47 (graphics38.png)

Therefore carrier concentration gradient in poly Si region is several times the carrier concentration gradient in Pure Silicon Emitter because mobility of hole in Pure Single Crystal Silicon region is several times greater than that in Poly Si on account of domain scattering in Poly region. Hence hole current crossing EB junction into Emitter is considerably reduced leading to a near unity Injection Efficiency. This leads to a much better α and hence a much better β . Now doping of base can be increased leading to a reduced base spreading resistance and hence better Figure of Merit and better Frequency Response without losing on current gain.

Section III.4. Base Spreading Resistance r x and the frequency response of BJT:

Base spreading resistance is due to the narrow sandwich of high sheet resistance P base. P Base is of 200 Ω/▄ to keep NA|B/ND|E = 1017/1019 as low as possible. This results in rx = 100 Ω. This creates serious deterioration in high frequency performance of BJT especially in terms of Unity Power Gain Frequency (fmax).

It can be shown that (fmax) = [fT/(8πrxCμ)]1/2

Using the dimensions of BJT used in 70s we get, we get

ft (Unity gain BW)= 624MHz;

fmax = [fT/(8πrxCμ)]1/2 = 18.6GHz;

From this example it is clear that base spreading resistance rx must be minimized to get best frequency performance but reduction of rx requires increased base conductivity but increased base conductivity means lower Injection Efficiency because

Injection Efficiency =γ = 1/[1+σBW/(σELp)]

From injection efficiency point of view: σB << σE;

These are contradictory requirements hence to achieve Short Circuit Current Gain of 100 we cannot allow Base Spreading Resistance to go below 100 ohm.

By using Poly Silicon , γ can be improved several orders of magnitude. This results in β of the order of 10,000. Here base conductivity can be increased to minimize Base Spreading Resistance. Thus with a reasonable β of 100, considerably lower Base Spreading Resistance can be achieved which plays crucial role in frequency performance and in improving the Figure of Merit of BJT which happens to be

GBP= 1/( rx Cμ);

Section III.5. Method of improving Emitter Injection Efficiency by Bipolar Hetero Structure.

Rewriting Equation XVIII we get:

Figure 48
Figure 48 (graphics39.png)

So if the EB junction is not a homojunction but a hetro junction

where (Eg|E- Eg|B)=0.15eV then βF = 400 even if (ND|E/NA|E) = 1 that is both E and B are equally doped. But (ND|E/NA|E) = 1 will drastically reduce Base Spreading Resistance which will leads to improved frequency response as well as improved GBP.

Graphically the improvement is evident as shown in the Graph:

Figure 49
Figure 49 (Picture 21.png)

Figure XI. In a HOMO JUNCTION of equal doping on two sides the total forward junction current is made up of 50% electrons being injected from N to P side and 50% holes being injected from P side to N side.

Figure 50
Figure 50 (Picture 22.png)

Figure XII. In a HETERO JUNCTION under forward bias the Built-in Barrier Potential are so unequal that Junction Current is wholly constituted of carriers injected from Wide Band Gap to Narrow Band Gap thereby automatically achieving 100% Injection Efficiency even without creating large doping differential on the two sides.

Thus we see that heterojunction are very naturally disposed towards giving 100% injection efficiency even with a very low base spreading resistance.

Section III.6. Fermi-level pinning and its prevention.


At Metal-ntype-Semiconductor interface we realize Schottky Barrier Diode. This exhibits a rectifying contact characteristic hence it has an in-built Schottky Barrier Height(SBH) as illustrated in Figure IV.1.

Figure 51
Figure 51 (Picture 23.png)

Figure XIII.. Asymptotic Energy Band Diagram of Metal-Semiconductor Interface and illustration of Schottky Barrier Potential Height.

It was found experimentally that SBH is insensitive to the Metal Work Function. This was defined as Fermi-Level pinning (FL pinning). It generally occurred at the mid-band gap of Semiconductor. This was always the case with polycrystalline MS interfaces and it was quite counterintuitive. In 1980s a few high quality, single crystal MS interfaces prepared and SBH measured. SBH was found to be sensitive to orientation/structure of MS interface. By spatially-resolved SBH measurement technique notably by Ballistic Electron Emission Microscopy(BEEM) it was found that SBH are inhomogeneous at polycrystalline MS interfaces and structure dependent at single crystal MS interfaces.

At the turn of the century when dipole associated with chemical bonding at MS interfaces was modeled using established methods borrowed from Molecular Physics it was shown that FL pinning was a natural consequence of interfacial bonding.

If minimization of total energy is applied

  1. then it results in structure dependence of SBH at epitaxial interfaces and
  2. SBH in homogeneity at polycrystalline interfaces.

By this theory FL pinning at polycrystalline MS interfaces and the pinning position at mid-band gap comes automatically.

This model is being further refined.

Section III.7. High-k solution for ULSI CMOS.[The high-k solution by Mark T. Bohr, Robert S. Chau, Tahir Ghani & Kaizad Mistry, IEEE Spectrum , October 2007, pp 23-29]

As the level of integration evolved, size of CMOS halved every 24 months. At this rate of scaling, by 1998 SiO2 gate insulation became 5 atomic layer thick with total thickness scaled to 13Aº each atomic layer being 2.6Aº. Current leakage and heating became a serious problem. Because of wave nature of electron and its quantum mechanical tunneling property, thin gate oxides allow the electrons accumulated on gate to leak to the channel. To overcome this problem we need physically thick gate oxides to prevent quantum mechanical tunneling but at the same time electrically thin so that channel is turned at low threshold. If dielectric constant is doubled then thickness can be doubled without any reduction in Turn-ON capability since C=kε0A/d

Figure 52
Figure 52 (graphics40.png)

where k=dielectric constant or relative permittivity of the gate insulator

d=thickness of the gate insulator and A= cross-sectional area of the gate insulator.

Metal interconnects are preferred over low-k material so that propagation delay is minimized.

Figure 53
Figure 53 (graphics41.png)

Low k will give higher velocity of propagation thereby minimizing the propagation delay.

MOS capacitance had to be reproducible, its behavior should be repeatable. To achieve this reproducibility and repeatability, Reactive Sputtering or Metal Organic CVD had to be abandoned in favour of Atomic Layer Deposition . This gave the necessary smoothness to the surface of the electrode as well as precise control over the thickness of the Gate Insulator. This ensured reproducibility and repeatability.

Several dielectrics were studied such as Al2O2 , TiO2 , Ti2O2 , Ti2O5 , HfO2 , HfSiO4, ZrO2, ZrSiO2, La2O3 .

With scaling due to Fermi-Level pinning , higher threshold Voltage (VThres) resulted. Also High-k material have high elasticity hence result in higher phonon scattering or lattice scattering resulting in lower channel mobility. By screening the phonon effect, the deterioration in channel conductivity could be prevented. This required increasing the electron density in Poly-Si gate. Hence we had to switch to Metal-High k combination. This prevented:

  1. Fermi-Level pinning hence threshold voltage normalized;
  2. This normalized channel conductivity which had drastically deteriorated due to dipole vibration effect;
  3. Metal Gate Electrode provides better bonding between Metal-Dielectric. Hence stable operation.

In mid-2003, Intel’s Hillsbaro, Ore, Development Fab developed HK-MG CMOS. Intel’s 130nm technology was used. Using Hafnium-Based Oxide and Metal Gate electrode following characteristics were achieved:

  1. Low Threshold = 1V;
  2. Negligible leakage current through Oxide;
  3. High 2-D channel mobility;

The standard fabrication method was “Gate First”. In this method:

Gate Dielectric+Gate Electrode were laid first;

Source and Drain implanted;

Silicon is annealed to repair the damages that occurred during ion-implantation. High Temperature became a problem for the new technology of HK-MG. So “Gate Last” technology was adopted which circumvented the annealing problem. This led to a paradigm shift in late 2004.

The new flow process was 45nm technology with High k + Metal Gate using Gate-Last strategy. Using this flow process in January 2006, 153Mb SRAM with 1 billion CMOS was built. Leakage gate current was reduced by a factor of 10. But there was sub-threshold leakage.

Scaling had reduced Threshold Voltage but reduced VTh led to increased sub-threshold leakage which defeated the nanoWatt-logic objective. Each new generation of scaled down transistor would increase ION by about 30% but would lead to Isub-threshold increase by 3-Fold. So at ULSI level, power efficiency and low leakage would be at premium rather than speed.

Table IV.The options at 45nm HK-MG CMOS Technology

Table 5
  Option 1 Option 2
Oxide thickness 13Aº 26Aº
ION 25% increase No increase
Isub-threshold No increase 1/5 Isub
VThres Same as before Increased threshold

The CMOS circuits are built between these two extremes.

PENRYN dual-core µP has 410mCMOS and PENRYN quad-core µP has 820 m CMOS. These are optimized for mobile applications, desk-top computers, 64-bit workstations and server applications.

Section III.8. Atomic layer Deposition

Dielectric Layers were deposited by Reactive Sputtering or by Metal Organic CVD. This left unevenness on the surface which caused charge trapping. There were charges stored at the interface too. These charges altered the behavior of MOS capacitance from discharge cycle to discharge cycle. So a deposition method had to be adopted which allowed dielectric deposition in controlled manner atom layer by layer.

Figure 54
Figure 54 (Picture 24.png)

Figure XIV. Methodology of Atomic Layer Deposition.

In Figure XIV the steps taken for Atomic Layer Deposition is illustrated. Gas1 reacts with bare Silicon surface to form a single atomic layer of insulator Si-Gas1. As soon as one layer is completed Gas1 stops reacting with Si because no bare Si is in contact with Gas1.

In step 2, Gas2 is chosen which is reactive with dielectric1 or Si-Gas1 insulator. Gas2 reacts with dielectric layer1 to form dielectric layer2 (Dielectric1-Gas2 insulator). As soon as dielectric layer2 covers the whole of dielectric1, reaction stops. Thus each reaction is terminated at the end of layer deposition. In this way we achieve layered gate insulator which is controllable down to the width of a single atom.

This produces much smoother dielectric hence the charge trapping is prevented . MOS produced is reproducible and stable in operation.

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