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Syllabus of EC1X61_IC Design and Fabrication Technology-Microelectronics [3-1-0]

Module by: Bijay_Kumar Sharma. E-mail the author

Summary: This module gives the syllabus of EC_1X61. The lecture notes covering this syllabus is given as Chapter 6 of Solid State Physics and Devices_The harbinger of third Wave of Civilization.

EC1661_IC Design and Fabrication Technology-Microelectronics [3-1-0]

Introduction – 50 years journey of IC Technology from micro to nano era_a broad overview.

Bipolar Junction Transistor Fabrication Process Flow; substrate preparation, oxidation process (wet and dry), photo-lithography, diffusion (pre-deposition and drive-in), buried layer diffusion_drive-in, Chemical Vapour Phase Deposition of thin Si epitaxial layer, isolation diffusion, base diffusion, emitter and collector pre-deposition diffusion, metallization for contact pads and interconnections, scribing of individual dies, mounting on ceramic wafers, ceramic wafers are bonded to headers, hermetic shielding and packaging (TO5 or Dual-in-Line package).

Diode, Resistance and capacitor realization by IC Technology.

BJT IC layout consideration.

MOS instability and C-V measurement curves under steady state DC voltages, ideal High-Frequency Capacitance and Low Frequency Capacitance.

Theoretical formulation of Threshold Voltage in MOS.

Comparative studies of BJT and MOS Technology.

Complete CMOS Process Flow:Ion –Implantation, LOCOS, Shallow Trench Isolation, Field –implant under LOCOS, Buried and Epitaxial layer option, LPCVD of Poly-Si gate, self-aligned Source and Drain, side-wall spacers along the edge of gate, source/drain LDD, multi-level interconnection-back end processing.

Using ATLAS and ATHENA carrying out the following simulations;

PN Junction Diode Simulation.

NPN BJT Simulation.

CMOS simulation.

Text Book: . Uploaded on SSPD_Chapter 6 by Bijay Kumar Sharma;

References: ”Silicon VLSI Technology: Fundamentals, Practice and Modeling”, Plummer, Deal and Griffin, Prentice Hall.

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