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SSPD_Chapter 7_Part 3_Basic Electrical Properties of MOS and MOS circuits to be continued1

Module by: Bijay_Kumar Sharma. E-mail the author

Summary: SSPD_Chapter 7_Part 3 gives the basic elecrical properties of MOS devices.

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SSPD_Chapter 7_Part 3_Basic Electrical Properties of MOS and MOS circuits.

7.3 The Output Characteristics of (Depletion)n-channel MOSFET.

Field Effect Transistors cover JFET and MOSFET. The underlying principle of FET is that there is a conducting channel which obeys Ohm’s Law:

Figure 1
Figure 1 (graphics1.png)

Where

Figure 2
Figure 2 (graphics2.png)

L = lemgth of the channel and A = cross-sectional area as shown in Figure 7.3.1.

And ρ = resistivity = 1/σ = 1/conductivity = 1/(qµnn);

Here q = charge of an electron, µn = mobility of an electron in the channel andn = conducting electron density in the n-channel.

Generally the n-channel is like a 2-D sheet hence its mobility is much lower than that in 3-D bulk. Typically µn = 1450 cm2/(V-sec) in Bulk Semiconductor and 650 cm2/(V-sec) in the channel in FET.

Figure 3
Figure 3 (graphics3.png)
.

As can be seen in the Figure 7.3.1 in n-channel FET electrons are being sourced from the source end and being drained out from the drain end. By corollary in p-channel FET holes will be sourced and holes will be drained out. This is the reason why the symbols are shown with the arrow of the conventional current flow. In nMOSFET conventional current is shown to come out of the Source and in pMOSFET conventional current is shown to enter into the Source as shown in Figure 7.3.2.

Figure 4
Figure 4 (graphics4.png)

Equation 7.3.1 is a linear equation with I-V characterisyics as shown in Figure 7.3.3.

Figure 5
Figure 5 (graphics5.png)

As seen in the Figure 7.3.3, I-V is linear for the whole range of voltage applied and is anti-symmetrical about the y-axis. Hence n-channel is a bilateral device where for positive voltage positive current flows and for negative voltage negative current flows with equal ease.

7.3.1. FET as a 3-terminal Device in Ohmic Region/Triode Region

Now by applying GATE voltage VGS transverse to the channel as shown in Figure 7.3.4 the channel thickness can be controlled and thereby the I-V slope can be controlled as shown in Figure 7.3.5.

Figure 6
Figure 6 (graphics6.png)

In this OHMIC REGION of operation, we have two cases. First case is when VDS is kept less than 0.1V. In this case channel remains a parrallaelopied with a reduced thickness ‘t’. In this case if we continue to apply more and more negative voltage, the channel will be eventually be completed depleted and we say that the channel has pinched off. The negative gate voltage at which this occurs is known as Pinch-Off voltage (VP).

There is a second case where VDS is greater than 0.1V and it continues to be increased. In this case the difference voltage between Gate and Drain > the difference between Gate and Source. Hence n-channel is trapezoidal and it does not give a linear I-V characteristics. This is also OHMIC REGION but non-linear. Linear and non-linear I-V curve is clearly indicated in Figure 7.3.5.

Figure 7
Figure 7 (graphics7.png)

As seen in Figure 7.3.4 and Figure 7.3.5 we have achieved Voltage –Controlled Resistance (VCR) but this VCR is not quite linear. At VDS < 0.1V, VCR is perfectly linear but at large VDS voltages the channel resistance deviates from the linear behavior.

In this kind of device at zero gate voltage, channel is present. Hence it is known as Normally-On . As the negative gate voltage is made more negative, the channel depletes until it finally completely pinches off . Hence it is known as .Depletion Type Device. As the gate voltage is made positive, channel becomes more conductive as it has a copious supply of electrons. Theefore we say that n-channel has enhanced.

All the above cases are Ohmic or Triode Region of operation of (D) n-channel MOS.

7.3.2. Saturation or Pentode Region of operation of (D) n-channel MOS.

For a given VGS , as VDS is increased a point comes when (VDS-VGS) = VP . At this point the channel gets pinched off on the Drain-side and n-channel becomes conical as shown in Figure 7.3.6. At this point let VDS = VDS*. Now the current IDS saturates.

Now if we increase VDS = VDS* +ΔV, the apex of the conical channel becomes more pinched off and the incremental voltage ΔV drops across the pinched off region between the apex of the cone and the drain. The voltage drop across the conical channel remains fixed at VDS* and the resistance of the conical channel is also constant at 1/3 of the full value of the parallaelopied channel resistance. Thus the drain current saturates at :

Figure 8
Figure 8 (graphics8.png)
7.3.2

Where R0 = the resistance of the parallaelopied channel.

The saturation region of operation or Pentode Region of operation is shown in Figure 7.3.7.

Figure 9
Figure 9 (graphics9.png)

All these arguments hold good for Enhancement Type MOSFETS also except that (E)nMOS is normally-off device and (D)nMOS is normally – on device. In Enhancement type NMOS, positive voltage has to be applied to the gate and only when Gate Voltage has exceeded the Threshold Voltage(VTh) that the n-channel is induced through inversion. In contrast in Depletion type NMOS, n-channel is already present there. Gate Voltage can be negative in which case the n-channel will get depleted and ultimately it will be pinched-off. Gate Voltage can be positive . In this case channel will beome more conductive.

(D)nMOS gives a greater flexibility of design hence it more preferred device.

Figure 10
Figure 10 (graphics10.png)

The Transfer Characteristics of (E)NMOS and (D)NMOS are shown in Figure 7.3.8. As can be seen from the Graph in Figure 7.3.8, (E)NMOS originates at VTh whereas (D)NMOS originates at pinch-off voltage VP . Both these transfer characteristics have been plotted in the Pentode region of the Output Characteristics. The saturation current of (D)NMOS at VGS = 0V is referred to as IDSS as it is done in JFET.

Figure 11
Figure 11 (graphics11.png)

Figure 12
Figure 12 (graphics12.png)

7.3.3.Theoretical Formulation of Output family of Curves of NMOS.

Just as in BJT,

Figure 13
Figure 13 (graphics13.png)

Where QB = charge stored in Base and τt = transit time in the Base.

Similarly

Figure 14
Figure 14 (graphics14.png)
7.3.3

Transit time has the following formulation:

Figure 15
Figure 15 (graphics15.png)
7.3.4

Drift Velocity of electron in the channel is as follows:

Figure 16
Figure 16 (graphics16.png)
7.3.5

Where µn = 2D mobility of electron in the channel because the channel behaves like a sheet and not like a Bulk.

Eds = Electric field from the Drain to Source

Figure 17
Figure 17 (graphics17.png)
7.3.6

Substituting Eq.7.3.6 in Eq 7.3.5 which in turn is substituted in Eq.7.3.4. we get:

Figure 18
Figure 18 (graphics18.png)

This is analgous to the expression we get for the transit time of electron in NPN BJT:

Figure 19
Figure 19 (graphics19.png)
7.3.8

Here W = effective Base width, µn = Bulk mobility of electron and VTh = thermal voltage at room temperature = kT/q;

7.3.3.1. Output Curve in Triode Region(non-saturated region).

Figure 20
Figure 20 (graphics20.png)

Figure 7.3.10 gives the 3-D view of NMOS transistor structure and it indicates the symbol used for the width, length of the channel anf for gate oxide thickness. According to the Figure:

L = length of the channel,

W = the width of the channel and D= thickness of the gate oxide.

We have to do the quantitative formulation of the n-channel charges induced in P-body after the Gate Voltage exceeds the threshold in case of (E)NMOS.

From now onward we will deal with (E)NMOS.

In (E)NMOS, positive gate voltage repels the majority carriers, namely holes, and creates depletion layer. In the process there is band-bending at the interface.

When band-bending = 2qψB then inversion layer is induced.

The charges on the two plates of the gate capacitance and the gate voltage is shown in Figure 7.3.11.

Figure 21
Figure 21 (graphics21.png)

Qg (the charge on the gate plate) = Qdmax (depletion layer charge at its maximum width) + Qi(inversion layer charge).

Qi = inversion layer charge is the channel charge which we have referred to as the charge induced in the channel = QC

QC = Dg(electric flux density terminating at the induced channel charge) ×WL

--------------------------------------------------------------------------------------------------------7.3.9

Total electric flux originating = Qg .

A part is terminating on (-ve)Qdmax and the remaining is terminating on (-ve)QC. The part which is terminating on (-ve)QC is accounted by Eq.7.3.9.

But Dg = Eg×εins×ε0

Where Eg = average gate electric field with respect to the channel,

εins = relative permittivity of the gate oxide = 4 for Silicon Dioxide ,

ε0 = free space permittivity or absolute permittivity = 8.854×10-14 F/cm.

To consider the average electric field (Eg), we must consider the average electric field of the channel.

The Drain end of the channel is at Vds and the source end is at 0V. Therefore the average voltage of the channel is (Vds/2).

Also effective gate voltage responsible for induced channel charges or responsible for inversion layer is (Vgs – Vt).

Hence average gate electric field with respect to the channel is:

Figure 22
Figure 22 (graphics22.png)
7.3.10

Where D = oxide thickness.

Therefore:

Figure 23
Figure 23 (graphics23.png)

But

Figure 24
Figure 24 (graphics24.png)

And

Figure 25
Figure 25 (graphics25.png)

Substituting Eq.7.3.11 and Eq.7.3.8 in Eq.7.3.3 we get:

Figure 26
Figure 26 (graphics26.png)

Gate Capacitance per unit area = Cox and total gate Capacitance is Cg therefore

Figure 27
Figure 27 (graphics27.png)

Equation 7.3.12 is also written as:

Figure 28
Figure 28 (graphics28.png)

This equation is applicable in non-saturated region where

Figure 29
Figure 29 (graphics29.png)

This non-saturated region is called ohmic region or triode region.

7.3.3.2. Output curves in Saturated Region (Pentode Region)

NMOS enters the saturated region when the trapezoidal channel pinches off from the drain side. This happens when

Figure 30
Figure 30 (graphics30.png)
7.3.15

Equation 7.3.14 reduces to:

Figure 31
Figure 31 (graphics31.png)
7.3.16

When Vds exceeds Vds*, still the voltage drop across the conical channel from the source to the apex of the cone remains Vds* and the excess voltage (Vds - Vds*) drops across the depleted region from the apex to the drain. By ballistic action electrons jump across the depleted region and maintain the current flow.

Equation 7.3.16 can be re-written as:

Figure 32
Figure 32 (graphics32.png)
7.3.17

As is evident from Eq. 7.3.17, the line of demarcation between Triode and Pentode is a parabola which was pointed out in the the family of output curves in Figure 7.3.7.

These equations describing the output family of curves are valid for (E)NMOS as well as for (D)NMOS except that in (E)NMOS threshold is a positive voltage typically 1V and in (D)NMOS it is a negative voltage typically -1V. Equation 7.3.14 and Equation 7.3.16 show that the electrical characteristics are critically dependent on the geometrical dimensions of the MOS devices.

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