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SSPD_Chapter 7_Part3_Electrical properties of MOS continued2

Module by: Bijay_Kumar Sharma. E-mail the author

Summary: SSPD_Chapter 7_Part 3 is the continuation of the Electrical Properties of MOS. In this module theoretical formulation of threshold voltage, transconductance, unity gain BW, output incremental conductance and figure of merit of NMOS is derived.

SSPD_Chapter 7_Part3_Electrical properties of MOS continued2

7.3.4. Theoretical Formulation of Threshold Voltage in (E)NMOS.

In SSPD_Chapter 6_Part 4_concluded_MOS and its Physics we have dealt with the theoretical formulation of the Threshold Voltage. The expression comes as follows:

Figure 1
Figure 1 (graphics1.png)

Where The Flat Band Voltage is = VFB = ϕm – ϕs = ϕm – [χ + Eg/(2q) + ψB]

χ = electron affinity in semi-conductor, Eg = energy band-gap of Silicon and ψB = potemtial diiference between Fermi-level(Ef) and intrinsic level(Ei) in Si-Bulk.

Therefore qVFB = qϕm – qϕs = qϕm – [qχ + Eg/(2) + qψB];

If source to bulk voltage (VSB) is not zero then this also has to be accounted. This is called Body Effect.

QSS = Qit (interface trapped charges) + Qot(oxide trapped charges) + Qm(mobile charges in the oxide) + Qf (fixed oxide charges).

Figure 2
Figure 2 (graphics2.png)

Generally substrate and source are connected together and threshold voltage is at the minimum.

But in certain applications, substrate is kept at reverse bias with respect to source. NMOS is built in P tub and PMOS is built in N tub.

Hence in NMOS, substrate is at negative bias with respect to source and in PMOS, substrate is at positive bias with respect to source.

Substrate bias gives rise to increase in threshold voltage. Hence Body-effect is represented by the following empirical expression:

Figure 3
Figure 3 (graphics3.png)

VTO = Threshold voltage with zero substrate bias;

And γ = body effect parameter (√V);

B = surface potential parameter.

Lower is the substrate doping, lower will be body effect.

The Typical values of Body effect is given in Table 7.3.1.

Table 7.3.1. Body effect in (E)NMOS and (D)NMOS

Table 1
Device Substrate biasVSB ThresholdVTh  
(E)NMOS 0V 0.2VDD 1V for VDD = +5V
  5V 0.3VDD 1.5V for VDD = +5V
(D)NMOS 0V -0.7VDD -3.5V for VDD = +5V
  5V -0.6VDD -3V for VDD = +5V

7.3.5. Theoretical formulation of Transconductance (g m )

Transconductance is the partial derivative of output current (Ids) with respect to input voltage (Vgs) with output voltage constant i.e. VDS is held constant.

Figure 4
Figure 4 (graphics4.png)

From Eq.7.3.3,

Figure 5
Figure 5 (graphics5.png)

And Transit Time is given by equation 7.3.7,

Figure 6
Figure 6 (graphics6.png)

Using these two equations incremental change in output current:

Figure 7
Figure 7 (graphics7.png)

But channel charge induced depends on gate capacitance and gate voltage:

Figure 8
Figure 8 (graphics8.png)


Figure 9
Figure 9 (graphics9.png)


Figure 10
Figure 10 (graphics10.png)

In saturation from Eq.7.3.15,

Figure 11
Figure 11 (graphics11.png)

Figure 12
Figure 12 (graphics12.png)
is the actual drop across the conical channel no matter what Vds is.

Hence in saturatin region:

Figure 13
Figure 13 (graphics13.png)
Figure 14
Figure 14 (graphics14.png)

From Eq.7.3.13 ,

Figure 15
Figure 15 (graphics15.png)

Substituting this in Eq.7.3.22:

Figure 16
Figure 16 (graphics16.png)
Figure 17
Figure 17 (graphics17.png)
Figure 18
Figure 18 (graphics18.png)
Figure 19
Figure 19 (graphics19.png)


Figure 20
Figure 20 (graphics20.png)
Figure 21
Figure 21 (graphics21.png)


Figure 22
Figure 22 (graphics22.png)
Figure 23
Figure 23 (graphics23.png)


Figure 24
Figure 24 (graphics24.png)

From Eq.7.3.23 it is evident that transconductance can be improved by reducing Channel Length.

Transconductance can be improved by increasing Channel Width. But both these methods have their drawbacks.

7.3.6. Theoretical Formulation of unity current gain band-width.

In BJT unity current gain band-width is defined as transit frequency ωT . It is derived by determining the Current Gain Band Width Product.

Short Circuit Current Gain is derived as:

Figure 25
Figure 25 (graphics25.png)


Figure 26
Figure 26 (graphics26.png)


Figure 27
Figure 27 (graphics27.png)

In exactly the same manner short circuit current gain of NMOS is derived and set to unity.

Figure 28
Figure 28 (Picture 1.png)
Figure 29
Figure 29 (graphics28.png)

Figure 30
Figure 30 (graphics29.png)


Figure 31
Figure 31 (graphics30.png)

Figure 32
Figure 32 (graphics31.png)

In Eq.7.3.25, ω0 = 5 ωu therefore, in working range of frequencies, Equation 7.3.25 can be simplified to:

Figure 33
Figure 33 (graphics32.png)

If Equation 7.3.26 is equated to Unity then its corresponding Unity Gain Frequency is:

Figure 34
Figure 34 (graphics33.png)

From Eq.7.3.27 it is evident that increase in transconductance gives a higher frequency range of opeartaion.

7.3.7. Theoretical Formulation of Output Conductance of (E)NMOS.

Theoretical expression of drain current in saturation region is given by Equation 7.3.16:

Figure 35
Figure 35 (graphics34.png)

As is evident from the above Equation, Ids has no dependence on Vds and Ids-Vds family of curves are perfectly horizontal and parallel to one another. Horizontal I-V curve implies infinite output impedance of the active device. But in practice it is not so. Real MOS devices have slopes in their family of I-V curves and this slope becomes pronounced as we scale the devices for the different generation of Technology. This is known as Channel Length Modulation effect.

In BJT we have Base Width Modulation also known as Early Effect. This Early Effect is the cause of the slope in output family of curves of CB BJT and CE BJT. Due to these slopes we have hob and hoe parameters in the two circuit configurations. Since Early Effect is more pronounced in CE BJT hence hoe = 1/40kΩ is greater than hob = 1/2MΩ. Channel Length Modulation is analogous to Early Effect and its degradation of family of output curves of NMOS is clealrly brought out in Figure 7.3.2. The physics of this degradation is that we have assumed that after saturation, Ids(sat) becomes constant at:

Figure 36
Figure 36 (graphics35.png)

In Equation 7.3.2 it is assumed that with increase in VDS, the voltage drop across the conical channel is constant at VDS* and excess voltage drops across the pinched off region. The second assumption is that the resistance of the conical section is constant at :

R0/3 where R0 is the resistance of the parallelopied channel.

This assumption does not remain valid with the scaling of devices. As the the device is scaled, the variation in Vds leads to significant change in the resistance of the conical channel because as pinched off region increases the axial length of the conical channel reduces and hence resistance offered decreases and IDS(sat) increases with the increase in VDS.

Figure 37
Figure 37 (Picture 2.png)

Channel Length Modulation is included in the saturated drain current in the following manner:

Figure 38
Figure 38 (graphics36.png)

Where λ = channel length modulation parameter which is dependent on channel length L and its typical values are:

Figure 39
Figure 39 (graphics37.png)
Figure 40
Figure 40 (graphics38.png)

Therefore the partial derivative of Ids with respect to Vds with gate voltage constant gives the the reciprocal of the incremental output resistance of (E)NMOS:

Figure 41
Figure 41 (graphics39.png)
Figure 42
Figure 42 (graphics40.png)

The overall dependence of 1/rds is :

Figure 43
Figure 43 (graphics41.png)

The incremental model of MOSFET incorporating transconductance and channel length modulation is given in Figure 7.3.1.

7.3.8. Figure of Merit of MOSFET.

The Unity Gain Bandwidth of MOSFET defines the Figure of Merit of MOSFET. Using Equation 7.3.27:

Figure 44
Figure 44 (graphics42.png)

Transconductance is given as:


Figure 45
Figure 45 (graphics43.png)
Figure 46
Figure 46 (graphics44.png)


Figure 47
Figure 47 (graphics45.png)

Gate Capacitance is given as:

Figure 48
Figure 48 (graphics46.png)

Substituting Eq.7.3.23 and 7.3.13 in Eq.7.3.31 we get:

Figure 49
Figure 49 (graphics47.png)

From Equation 7.3.7

Figure 50
Figure 50 (graphics48.png)

Therefore Figure of Merit is the reciprocal of the transit time across the channel.

Larger is the electron mobility, better will be the Figure of Merit. Hence <100> orientation Si Substrate is chosen for fabrication of CMOS circuis. The mobility of electron and hole is always much larger in <100> orientation substrate than that in <111> orientation substrate. In Table 7.3.2 a comparative study of the electron mobility in <111> and <100> substrate is given.

Table 7.3.2. Comparative study of mobilities in <100> and <111>orientation substrate in thin channel and in bulk.

Table 2
  Bulk mobility<100> 2D channel mobility<100> 2D Channel mobility<111>
µn 1250cm2/(V-sec) 650 cm2/(V-sec) 500 cm2/(V-sec)
µp 480 cm2/(V-sec) 240 cm2/(V-sec) 216 cm2/(V-sec)

For fast CMOS circuits fabrications, <100> Si Substrate is the choice of material in Industries.

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