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# SSPD_Chapter 7_Part 3_Electrical Properties of MOScontinued3

Module by: Bijay_Kumar Sharma. E-mail the author

Summary: SSPD_Chapter 7_Part 3_Basic Electrical Properties of MOS coninued3 is the continuation of Electrical Properties of MOS. This describes that the proper circuit working is critically dependent on the correct geometrical dimensions of MOS transistors.

SSPD_Chapter 7_Part 3_Electrical Properties of MOScontinued3

7.3.9 MOS as an Analog Switch- Pass Transistor.

Just as electro-magnetic Relay Switches can be used to form Logic Gates. In a similar fashion, MOS can be used as analog switches to form Logic Gates. The use of Relay Switch is shown in Figure 7.3.9.1 and use of MOS is shown in Figure 7.3.9.2.

When MOS transistors are used as analog switches they are called Pass Transistors.

Here Logic 1 is VDD – Vth.

7.3.10. RTL Inverters.

RTL Inverters was the earliest building block of digital systems. It evolved to TTL gate. It further evolved to NMOS. Today CMOS Inverters have become the basic building block of most digital systems having much more superior performance characteristics as compared to the original RTL Inverter. A RTL Inverter is shown in Figure 7.3.10.1.

In Figure 7.3.10.1, part (A) gives the circuit configuration. Part (B) gives the DC load line superimposed over the output family of curves. From the intersection of the DC Load Line and the output I-V curve corresponding to Vin = 0V(Low condition) and Vin = 5V(High condition) we obtain two Q points. Table 7.3.10.1 gives the two Q points.

Table 7.3.10.1 The two Q points corresponding to I/P low and I/P high.

 DC operating points or Quiescent points Vin Vce = Vout Ic Q1 5V 0.2V=Vce(sat)O/P=LOW Vcc/Rc Transistor is driven into saturation Q2 0V VccO/P=HIGH 0mA Transistor is cut-off

Part(C) gives the transfer characteristics and Part (D) gives the noise margin. As is evident from Figure (D), noise margin can be maximized by reducing the transition region and this precisely what happens in CMOS inverter. In CMOS Inverter, transition region is 0 V and

The central point of this brief review of RTL Inverter is to illustrate the principle by which Transfer Characteristics is arrived. We draw the load line over the family of output curves, determine the Q-points for the two binary states of Input and from the Q-points we arrive at the transfer characteristics of the Inverter. From the transfer characteristics we arrive at the noise margin. This is the procedure we will adopt to arrive at the performance characteristics of the subsequent inverters.

7.3.10.1. The NMOS Inverter.

MOS inverters are synthesized in the same manner as RTL Inverter in Figure 7.3.10.1. Since passive resistances are difficult to integrate as they occupy a large area on silicon die hence passive resistive loads are an anathema for ICs . The passive loads have been completely replaced by active loads. In Figure 7.3.10.2, an NMOS inverter is shown.

In the NMOS inverter, (E)NMOS acts as the inverter driver which is called the pull-down transistor and (D)NMOS acts as the active load of the driver also known as pull-up transistor. First we will examine how (D)NMOS acts as resistive active load of the logic circuit.

(D)NMOS is transistor 2 which acts as the load to the driver transistor 1. Load (D)NMOS has its Gate shorted to Source hence VGS = 0V curve applies to the load I-V characteristics which is shown in the lower graph in isolation. It is a non-linear resistance accordingly the load line produced on the output plane of driver transistor (E)NMOS is also non-linear as shown in Figure 7.3.10.4. The slope of the load line is primarily determined by the Triode Region of (D)NMOS.

At low Vds the above equation reduces to:

Therefore:

W 2 /L 2 = aspect ratio of the active load or transistor 2.

In Figure 7.3.10.4., the non-linear load line is drawn on the output plane of (E)NMOS and the intersection of the load line and the output curve under input high condition and under input low condition gives us the two Q points of the driver transistor as shown in Table 7.3.10.2..

Table 7.3.10.2 The two Q points corresponding to I/P low and I/P high.

 Q point Vin Vds(T1) Id(T1) (d) +4V Vds(LOW) Ids* T1 is ON T2 is ON (a) 0V Vdd 0mA T1 is OFF T2 is ON.

The triode portion of the output curve corresponding to VGS(T1) = +4V determines Zpd.

From Equation 7.3.14, Zpd is derived to be:

From Figure 7.3.10.4, we can extract the inverter transfer characteristics. The point of intersections between the load line and output curves corresponding to different values of input voltage = gate voltage give the transfer characteristics of the inverter as tabulated in Table 7.3.10.3 and shown in Figure 7.3.10.5.

Table 7.3.10.3

 Vin 0 2.5V 3V 4V Vout 5V 3V 2V 0.75V

This transfer characteristics and inversion pont is sensitive to geometrical variations in W and L and to the variation in the ratio of pull-up to pull-down resistances ratio as shown in Figure 7.3.10.6. The point where the locus of Vin = Vout and Transfer Characteristics intersect is called the inversion point(Vinv). We have the best Noise Margin if Vinv = 0.5Vdd.

.

7.3.10.2. Theoretical formulation of Pull-Up to Pull-down resistances for different configurations.

There can be two configurations of NMOS Inverter. Inverter can be driven by a preceding inverter or it can be driven by a Pass Transitor as shown in Figure 7.3.10.7.

Refer to Figure 7.3.10.2. For best noise margin we choose Vin = Vinv = 0.5Vdd. At this point both the transistors are in Saturation Region(Pentode Region). In Pentode Region the following equation is applicable:

7.3.16

IDS2 = IDS1.

Substituting the appropriate vales in Eq.7.3.16 we get:

Let

Making the proper substitutions we obtain:

Further Simlification yields:

By substituting the typical values of different parameters namely:

Vt = 1V, Vtd = -3V, Vinv = 2.5V (for equal noise margin) we get:

7.3.10.1.4

7.3.10.2.1. Pull-Up to Pull-down ratio when NMOS Invereter is driven through pass transistors.

The second arrangement in Figure 7.3.10.7 is an NMOS Inverter driven by one or more pass transistors. Here the signal while being transmitted through Pass Transistor will get degraded (Vdd gets reduced to [Vdd-Vtp]) and may give erroneous result. The requirement is that the degradation of the signal by Vtp should not effect correct signal processing This implies that

Inverter 1: Vin=Vdd gives Vout=0.75V and for

Inverter 2:Vin=Vdd-Vtp should also give Vout=0.75V.

Table 7.3.10.4 gives the states of the 4 transistors in the two inverters 1 and 2 when driven by Vdd and [Vdd-Vtp] respectively.

Table 7.3.10.4. The states of the 4 transistors in the two inverters 1 and 2 when driven by Vdd and [Vdd-Vtp] respectively.(Refer to Figure 7.3.10.4)

 Inverter Vin pd(T1) Vout pu(T2) 1 Vdd ON in Triode region 0.75V ON in Pentode region 2 Vdd-Vtp ON in Triode region 0.75V ON in Pentode region

For Inverter1, in pd(T1):

Since Vds1= 0.75V therefore Vds1/2 can be neglected and the expression of R1 is as follows:

For the load, VDS2 = 4.25V hence puT(2) is in Pentode region with Vgs = 0V.the transistor current I is:

Here Zpd1 and Zpu1 refer to the transistors in Inverter1. The circuit model for this I/P high is shown in Figure 7.3.10.8. pd(T1) is represented by R1 and pu(T2) is represented by a current source IDS2.

But IDS1 = IDS2 therefore;

Substituting the values of R1 and IDS2 from above we get:

Consider Inverter 2: when Vin = V DD -V tp .

We do exactly the same calculation as for Inverter1.

Pull-down NMOS is R2.

Pull-up NMOS is Saturated.

Therefore Vout2 of Inverter 2 with Vin = VDD – Vtp is given as:

If the pass transistor introduces no degradation in operation then in both the inverters we should get the same output even though the second inverter is receiving a degraded Input for High condition.

Therefore

Therefore

Substiturting the defacto values:

Vt = 0.2VDD =1V and Vtp = 0.3VDD =1.5V

We get:

Or

Or

We saw that Inverter driven directly by Inverter should have

Inverter driven through a pass transistor should have:

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