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SSPD_Chapter 7_Part 3_Basic Electrical Properties of MOSFET_continued8

Module by: Bijay_Kumar Sharma. E-mail the author

Summary: SSPD_Chapter 7_Part 3_Basic Electrical Properties of MOSFET_continued 8 gives the configuration of BiCMOS inverter and its optimized version.

SSPD_Chapter 7_Part 3_Basic Electric Properties of MOSFET_Continued_8

7.3.15. BiCMOS Inverters.

Figure 1
Figure 1 (graphics1.png)

In the output stage where loads have to be driven, CMOS Logic Gates themselves cannot give adequate current for drivng the loads. In these circuits buffer BJT are added as shown in Figure The inverted logic operation is carried out as shown in Table

Table The Inverted Logic Operation of BiCMOS inverter.

Table 1
Input Q1 Q2 Q3 Q4 Vout
LOW(GND) off On and Q2 sources current to charge CL to 5V through a low impedance path provided by on BJT Q2 off on HIGH=5-VBE(on)
HIGH(5V) On and Q1 sinks current thereby discharging CL through low impedance path provided by on BJT Q1 off on off LOW = VCE(sat)

The characteristics of BiCMOS Inverter.

i.Logic levels are close to bus voltages;

ii.High input impedance;

iii.Low output impedance;

iv. It has high current drive capability and occupies a relatively small area;

v. It has large Noise Margin.

But this configuration has high standby dissipation under I/P = HIGH condition since Q1 and Q3 provide a low impedance path from Positive Bus to GND bus.

Also this configuration has no path for turning off the BJT when required.This slows the switching operation. Hence we go for improved circuit configuration.

Figure 2
Figure 2 (graphics2.png)

In Figure we have removed the direct dc path from Positive Bus to GND through Q3 and Q1 but when Vin = HIGH, Vout ≠ VCE(sat) which is 0.2V but Vout = VBE(on) = 0.7V. Hence output swing is reduced from full 5V to about 4V.

Also BJTs still donot have a discharge path for their base currents during turn off of the respective BJT. So a third configuration is given in Figure

Figure 3
Figure 3 (graphics3.png)

In the improved version shown in Figure two resistances R1 and R2 are introduced in the discharge paths of the bases of the BJTs , Q1 and Q2. Because of the resistances, the logic levels are improved and hence voltage swing is optimized. The resistances also speed up the switching of the transistors.

Though this is an improved version of BiCMOS Inverter from IC technology point of view it is impractical because passive chip resistances occupy large real estate area and suitable values are difficult to realize. Hence chip resistances are replaced by MOS transistors as shown in Figure

In Figure, the function of R1 is fulfilled by Q5 and function of R2 is fulfilled by Q6. The states of different transistors during Inverted Logic Operation are given in Table

Table Inverted Logic Operation of the optimized version ogf BiCMOS.

Table 2
Vin Q1 Q2 Q3 Q4 Q5 Q6 Vout
HIGH SAT OFF ON OFF ONThis provides the discharge path for the base current of Q2 which was ON previously OFF LOW=VCE(sat)
LOW OFF ON OFF ON OFF ONThis provides the discharge path for the base current of Q1 which was in SAT previously HIGH
Figure 4
Figure 4 (graphics4.png)

This circuit offers enormous advantages where high load current sourcing and sinking are required. Whenever Video Monitors or Speakers are to be driven there we require BiCMOS interface at the output.

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