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Summary: Chapter 7_Part 3_Conclusion module concludes the basic electrical properties of MOSFET by discussing the latch-up problem and its remedies.
SSPD_Chapter 7_Part 3_Basic Electrical Properties of MOSFET_concluded.
7.3.16. Latch-Up problem in CMOS and its remedy.
[This part is adapted from the lecture series of Steve McGarry,Department of Electronics, University of Carleton, Ottawa. e-mail:smcgarry@doe.carleton.ca]
CMOS logic is fabricated either by P-Well or N-Well Process or by Twin-Well Process. In any of these processes we have a large number of junctions as . In Figure 7.3.16.1. we give the cross-sectional view of CMOS fabricated by N-Well process. These multiple junctions give rise to three-junction four-layer device which behaves like a SCR. This we call parasitic SCR.
This arises due to cross coupling of P+NP and N+PN transistors. How these parasitic transistors action arise is shown in Figure 7.3.16.2.
If this parasitic SCR is turned ON by the glitches on the power bus or by irradiation, then a low resistance conducting path is created between Positive Voltage Bus (VDD) and GND Bus (VSS). This causes irreversible damage to the IC chip. This precisely is SCR Latch-Up problem in CMOS. By careful control during fabrication, the parasitic SCR can be prevented from latching up under all conditions.
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In MOS structures the source is always shorted to the body. As seen in the above Figures, Source of NMOS i.e. N+S is connected to P+body by a metal interconnect and P+body makes an ohmic contact to P-substrate. Similarly Source of PMOS i.e. P+S is connected to N+body by a metal interconnect and N+body makes an ohmic contact to N-Well. This ensures that Source-Body bias is zero which leads to zero BODY EFFECT hence threshold voltage of the MOS is held constant.
The equivalent circuit model is given in Figure 7.3.16.3.
As seen in the Figure, the positive voltage bus acts as the Anode of the parasitic SCR and the GND bus i.e. VSS bus acts as the Cathode of the parasitic SCR. For discussion purpose we assume that Rsubstrate and Rwell are infinite. Under normal condtions voltage between the two buses is 5V or less hence SCR doesnot fire and there is no latching.
7.3.16.1. Why does SCR fire above break-over voltage ?
By inspection of the Circuit Model of SCR in Figure 7.3.16.3 we get the following equations:
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We further see that:
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Where ICBO = Collector-Base Junction reverse leakage current with Emitter open.
Adding the two above equations, we get:
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By rearranging the terms we get:
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We know that IE1 = IE2 = IE by Kirchoff’s Current Law;
Also IC1 + IC2 = IE2 = IE ;
Therefore rearranging the terms we get:
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Forward Current Transfer Ratio of BJT is αF = γ×β*×M
Where γ = injection efficiency. It falls at low currents due to recombination in depletion layer and it also falls at high current due to conductivity modulation. It is at the maximum value at moderate currents.
Also β* = base transport factor. This improves as Base Width becomes narrower which it will at higher voltages of VCE(forward active mode).
M= Avalanche Multiplication Factor which does not come into picture at low voltages.
Initially αF is very small due to very low currents flowing through it but as VAK (voltage between anode and cathode) increases, due to shrinking of Base width both alphas improve.
At αF1 + αF2 = 1, the current increases in a runaway fashion only limited by the external resistance. This is the firing point of the parasitic SCR embedded in the CMOS structure and can do irreversible damage to the IC.
7.3.16.2. How does the runaway process of SCR current set in?
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As we see in Figure 7.3.16.5. Step 8 a positive feed back loop or regenerative loop is set up.
A transient at P+Drain of PMOS sets up a hole current through Rsub which triggers N+drain of NMOS to set up an electron current through Rwell.
The electron current through Rwell further enhances hole current through Rsub and hole current through Rsub further increments the electron current through Rwell. This leads to a runaway condition which results in a large current flow from VDD bus to VSS bus and subsequently damages the CMOS structure.
7.3.16.3. The remedies of Latching Problem in N-Well process/P-Well process.
Design approach.(internal implants and larger spacing)
As we see in Figure 7.3.16.5. Step 8, we have two BJTs Q1 and Q2.
Q1 is comprised of P+(drainof PMOS)-Nwell-Psubstrate and Q2 is comprised of N+(drain of NMOS)-Psubstrate-Nwell.
Q1 current gain can be reduced by introducing a buried layer in N-Well. This reduces the injection efficiency.
Q2 current gain can be reduced by increasing the spacing between N-Well and N+ Source/Drain. Increase in the spacing leads to reduced Base Transport Factor.
Fabrication approach.
As we saw in our discussion, Rsub and Rwell play a crucial role in setting up the runaway process. If by chosing higher doping level we reduce Rsub and Rwell then also runaway process will be prevented
Guard rings around N-Well with frequent contacts to the rings reduces the parasitic resistances. This also prevents the latch-up. The CMOS layout plan view is shown in Figure 7.3.16.6 and in Figure 7.3.16.7. without and with guard ring respectively.
7.3.16.4. Prevention of Latching in Twin-Tub Process.
In Twin-Tub process by the formation of ‘Refilled Trench Isolation’ between Twin Tub.This isolation prevents formation of parasitic BJT as shown in Figure 7.3.16.8.
The trench is formed in Silicon Substrate by anisotropic reactive sputter etching. Oxide layer is grown on the side-walls and bottom of the trench. This oxide lined trench is filled by Poly-Si or SiO2 . This kind of structure is shown in Figure 7.3.16.8.
The trench isolation disrupts the parasitic BJT hence parasitic SCR is prevented structurally as shown in Figure 7.3.16.8
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7.3.16.5. BiCMOS Latch-up susceptibility.
BiCMOS is less susceptible to latch-up problems because it has less substrate body resistance (Rsub) and less n-well body resistance (Rwell). Hence it requires larger currents through Rsub and Rwell to trigger latch-up process.
A typical BiCMOS in N-well process is shown in Figure 7.3.16.9
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As can be seen from Figure 7.3.16.9 there is parasitic vertical PNP transistor constituted of
P base, N-Well and Psubstrate. This is a part of the N-Well Latch-up circuit. Due to the presence of N+BCCD(buried N+ subcollector), the life-time of minority carriers in the base of the parasitic vertical PNP is reduced. This reduces beta of the vertical PNP transistor since beta = life-time of minority cariers/ transit time. Hence latch-up susceptibility is reduced.
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Last edited by Bijay_Kumar Sharma on Jun 28, 2011 8:42 am -0500.
