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# SSPD_Chapter 7_Part 6_Basic Circuit Concepts.

Module by: Bijay_Kumar Sharma. E-mail the author

Summary: SSPD_chapter 7_Part 6 introduces the concept of Sheet Resistance and Capacitance per Unit Area. From the basic circuit concepts we can arrive at the absolute values of the circuit elements which help in modeling the circuit behaviour.

SSPD_Chapter 7_Part 6_Basic Circuit Concepts.

7.6.1. Sheet Resistance.

Referring to Figure 7.6.1 we see that:

Resistance of the slab along the longitudinal axis:

Therefore

Table 7.6.1 gives the typical values of the sheet resistance of the different layers of CMOS IC circuit.

Table 7.6.1.Typical values of the sheet resistance RS of MOS layers for technology generation 5μm, 2μm and 1.2μm. (Here 5μm, 2μm and 1.2μm imply the minimum feature size = channel length for the given technology . Consequently λ is 2.5μm, 1μm and 0.6μm for these three generations respectively).

 Layer RS(Ω/square) 5μm 2μm 1.2μm Metal 0.03 0.04 0.04 Diffusion 10→50 20→45 20→45 Silicide 2→4 Poly_Si 15→100 15→30 15→30 N channel 104 2×104 2×104 P channel 2.5×104 4.5×104 4.5×104

7.6.1.1. Resistance calculation of N-Channel in 5μm Generation of Technology.

If L:W = 2λ:2λ then Rchannel = Rsheet×(L/W) = 1×104Ω..

If L:W = 8λ:2λ then Rchannel = Rsheet×(L/W) = 1×104Ω.×4 =4×104Ω..

With scaling, feature size has decreased and the pitch of metal interconnect has decreased. This has led to excessive RC time delay. To control this, metal interconnects are being replaced by Metal Silicides. The metal silicides or the refractory silicides are formed by depositing metal on poly-silicon and then sintering it. Though these have proved to be successful substitutes of metal interconnects the extra processing steps make it uneconomical.

With scaling the cross-sectional area of the metal interconnect decreases and current density increases. As this exceeds the limit of 1.5mA/mm, metal grains are pushed around and wire interconnects break. This is called migration. Silicides prevent electron migration.

With the latest generation of technology, silicides are being further replaced by copper interconnects.

7.6.2. Area Capacitance of Layers.

Parallel plate capacitance is given by the formula:

Where D=thickness of the dielectric between the plates;

A = cross-sectional area of the plate;

Absolute permittivity (permittivity) = ε0 = 8.85×10-14 F/cm;

Relative permittivity of the dielectric in this case SiO2 = 3.9;

In VLSI design we express Capacitance per unit area = (pF/μm2). To obtain it in this form we have to the scaling factor as follows:

But Gate-to-Channel capacitance, Cg (pF/μm2) = 4×10-4, 8×10-4, 16×10-4 ;

Therefore D = 88.5nm, 44.27nm, 22.1nm

Typical values are given in Table 7.6.2.

Table 7.6.2. Typical area capacitance values for MOS cuircuits.

 Capacitance Value in pF×(10-4/μm2) (relative value in brackets) 5μm 2μm 1.2μm Gate Oxide Thickness 88.5nm 44.27nm 22.1nm Gate to Channel 4 (1.0) 8 (1.0) 16 (1.0) Difusion(active) 1 (0.25) 1.75 (0.22) 3.75 (0.23) Poly-Si to substrate 0.4 (0.1) 0.6 (0.075) 0.6 (0.038) Metal 1 to substrate .3 (0.075) 0. 33 (0.04) 0.33 (0.02) Metal 2 to substrate 0.2 (0.05) 0.17 (0.02) 0.17 (0.01) Metal 2 to metal 1 0.4 (0.1) 0.5 (0.06) 0.5 (0.03) Metal 2 to poly-Si .3 (0.075) 0. 3 (0.038) 0.3 (0.018)

7.6.2.1. Calculation of Standard Unit of Capacitance □C g

Generally while designing we donot work in terms of absolute values of capacitances. Instrtead we work in relative terms with repect to some standard value and the absolute value of that standard is recorded accurately.

In the present case the gate-to-channel capacitance of a MOS transistor with W=L=2λ is calculated fot the different generations of technology and this is refered to as □Cg. Table 7.6.3 gives the values of □Cg for three generations of technology namely 5μm, 2μm and 1.2μm.

Table 7.6.3. Standard Unit of Capacitance for 5μm, 2μm and 1.2μm Generation.

 5μm 2μm 1.2μm Gate-to-Channel 4 pF×10-4/μm2 8 pF×10-4/μm2 16 pF×10-4/μm2 □Cg (5μm×5μm)×4 pF×10-4/μm2= 0.01 pF (2μm×2μm)×8 pF×10-4/μm2= 0.0032 pF (1.2μm×1.2μm)×16 pF×10-4/μm2 = 0.0023 pF

In Table 7.6.4 the oxide thickness is given for different Generations of Technology.

Table 7.6.4 Oxide Thickness scaling with channel length scaling.

 L 5 μm 2 μm 1.2 μm 90nm 45nm 30nm D 88nm 44nm 22nm 1.3nm=5atomic layers

As oxide becomes thinner, current leakage through the oxide layer by means of quantum tunneling and consequent heating becomes a serious problem. We need physically thick oxide to prevent the leakage and electrically thin to keep the threshold Voltage low. Rewriting Eq 7.6.2.1 we get:

By inspection of the above Equation we see that if relative permittivity is doubled in the numerator then thickness of the oxide layer,D, will also double thus making the Gate dielectric layer thick enough to prevent leakage aand leaving the threshold voltage unaffected.

Along with vertical scaling, lateral scaling has taken place. This has led to reduction in cross-sevtional area ‘A’. This decreases Capactance C and increases threshold voltage.. If threshold voltage has to be maintained around 0.5V then the thickness D will once again have to be decreased.

Therefore High K-metal gate was introduced. High K made the oxide layer thicker and metal gate prevented Fermi level pinning..

7.6.2.2. Metal 1 to Substraate Area Capacitance Calculation for 5μm Generation.

In Figure 7.6.2, the cross-sectional view and the plan view of a metal interconnect is shown.

The length by breadth of the metal track =(L=20λ×W=3λ) is given. Determine Metal 1 to Substrate area capacitance in terms of the standard capacitance.

From Table 7.6.1, for 5μm Generation of CMOS:

Metal 1 to substrate capacitance per unit area = 0.075×□Cg

Therefore total area relative capacitance :

Therefore Total area capacitance between metal 1 and substrate

=15×0.075×□Cg = 1.125□Cg

The absolute value of the interplate capacitance

between metal 1 and substrate=1.125×0.01pF=0.0125pF.

Similarly same area between poly-Si and substrate= 15×0.1×□Cg=1.5□Cg ;

Same area between n-type diffusion and substrate =15×0.25×□Cg=3.75□Cg ;

7.6.2.3 Capacitance calculation in multi layer structures.

A CMOS IC with multi-layer metal interconnect is shown in Figure 7.6.2.2 and in Figure 7.6.2.3. plan view of metal interconnect making contact with Poly-Si extension from the gate is shown.

It should be noted that Poly-Si over the Gate lies over 88.5nm thin oxide layer has the nomenclature of Gate-to-Chanel and has the standard value of 1□Cg on the other hand

Poly-Si over the remaining portion runs over 5μm thick oxide layer and has the nomenclature Poly-Si-to-Substrate and has the value of 0.1□Cg.

In Figure 7.6.2.3 we are required to determine Metal interconnect-to-Substrate capacitancve, Poly-Si-to-Substrate capacitance excluding Gate, Gate capacitance and total capacitance are to be calculated.

Relative area of metal interconnect with respect to standard capacitance =(100λ×3λ)/(2λ×2λ) = 75

Therefore Metal interconnect-to-Substrate Capacitance = 75×0.075□Cg = 5.625□Cg;

C m = 5.625□C g ;

Poly-Si-to-Substrate Capacitance(excluding Gate area)

=[(overlap area + extension area of Poly-Si excluding Gate)/(2λ×2λ)]×0.1□Cg

=[(4λ×4λ +3λ×3λ)/ 2λ×2λ)]×0.1□Cg=0.55□Cg;

C poly = 0.55□C g ;

C gate = 1□C g ;

Therefore Ctotal = Cm + Cpoly + Cgate =(5.625+0.55+1) □Cg = 7.175□Cg;

The absolute value is Ctotal = 7.157×0.01pF=0.0717pF for 5μm Generation.

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