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SSPD_Chapter 7_Part 6_Basic Circuit Concepts_continued 3

Module by: Bijay_Kumar Sharma. E-mail the author

Summary: SSPD_Chapter 7_Part 6_Basic Circuit Concepts_continued 3 calculates the rise time and the fall timne and proves that for symmetric switching PMOS width must be 2.5 times wider than NMOS width.

SSPD_Chapter 7_Part 6_Basic Circuit Concepts_continued 3

7.6.4. Formal Estimation of CMOS Inverter delay.

In Figure 7.6.4.1 we show a CMOS Inverter being driven by square wave and loaded with input capacitance of the subsequent stage. We model the CMOS Inverter during switching transients by constant current source driving the load capacitance.

Figure 1
Figure 1 (Picture 1.png)

The switching transient is shown in Figure 7.6.4.2.

Figure 2
Figure 2 (Picture 2.png)

As can be seen in Figure 7.6.4.2, during HIGH to LOW switching NMOS (Qn) provides the low impedance path to ground and hence sinks the discharge current. Hence saturation current of NMOS provides the ID .

Similarly during LOW to HIGH switching PMOS (Qp) provides the low impedance path from VDD bus to the load capacitance and hence sources the charging current. Hence saturation current of PMOS provides the IC .

Referring to the circuit model in Figure 7.6.4.1 we see that:

Rate of change of capacitance voltage = Constant Current/C

Therefore:

Figure 3
Figure 3 (graphics1.png)

Therefore:

Figure 4
Figure 4 (graphics2.png)

Therefore:

Figure 5
Figure 5 (graphics3.png)

During output HIGH to LOW transient: NMOS (Qn) is sinking the current from the load capacitance hence constant current source is a discharge current ID coming as the saturation current of NMOS where

Figure 6
Figure 6 (graphics4.png)

During output LOW to HIGH transient:PMOS(Qp) is sourcing the current to the load capacitance hence constant current source is a charging current IC coming as the saturation current of PMOS where

Figure 7
Figure 7 (graphics5.png)

But ∆VC = VDD , VGS = VDD and VT = 0.2 VDD therefore

Figure 8
Figure 8 (graphics6.png)

Substituting Eq.7.6.4.6 in Eq 7.6.4.4 and Eq.7.6.4.5 we get:

Figure 9
Figure 9 (graphics7.png)
Figure 10
Figure 10 (graphics8.png)

Dividing Eq 7.6.4.8 by Eq.7.6.4.7 we get:

Figure 11
Figure 11 (graphics9.png)

From Basic Electrical Properties we know that

Figure 12
Figure 12 (graphics10.png)

From Device Physics we know that

Figure 13
Figure 13 (graphics11.png)

We also know from section 7.3.12 titled ‘optimization of geometric parameters to achieve the beswt CMOS performance’ that :

Figure 14
Figure 14 (graphics12.png)

Substituting the two conditions stated by Eq.7.6.4.8 and Eq.7.6.4.9 in Eq 7.6.4.7 we get

Figure 15
Figure 15 (graphics13.png)

Eq 7.6.4.10 implies that we will get symmetric switching transients as well as maximum Noise Margin if satisfy the condition stated in Eq 7.6.4.11 namely

Figure 16
Figure 16 (graphics14.png)

Hence CMOS layout will be as shown in Figure 7.6.4.3 for optimum performance in all sense of the word i.e in the sense of switching transient and in the sense of noise margin.

Two alternative layouts are shown in Figure 7.6.4.4.

In all the three figures, where metal has to connect to Poly-Si or to n-channel or to p-channel there a contact has to be made symbolized by black cross.

Figure 17
Figure 17 (Picture 3.png)

Figure 18
Figure 18 (Picture 4.png)

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