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# SSPD_Chapter 7_Part 6_Basic Circuit Concepts_concluded

Module by: Bijay_Kumar Sharma. E-mail the author

Summary: SSPD_Chapter 7_Part 6_Basic Circuit Concepts_concluded This module concludes the basic circuit concepts by giving the analysis of the parasitic capacitances associated with fringing-field effect, with interlayer effect,with inter-wire effect,with overlap effect and with peripheral effect.Including these parasitics makes the modelling and simulation more acurate and hence more realistic.

SSPD_Chapter 7_Part 6_Basic Circuit Concepts_concluded

7.6.9. Wiring Capacitances.

We have already discussed area capacitances and its effects on the speed of switching. Here we will discuss the various parasistic capacitances associated with the interconnection wirings. These need to be accounted along with the area capacitances while studying the performance of CMOS circuits. Three main sources of wiring parasitic capacitances are: fringing fields, interlayer capacitances aand peripheral capacitances.

7.6.9.1.Fringing Fields.

In any area parallel-plate capacitance there are transverse field lines as well as fringing field lines which can be significant fraction of the transverse field line as shown in Figure 7.6.9.1. In the standard parallel plate formula (εA/d) which is used for area capacitance calculation we account for transverse field only. To consider the total capacitance we need to calculate the Capacitance due to fringe field.

Where

It is given:

FF is plotted in Figure 7.6.9.2.

From the graph in Figure 7.6.9.2 it is evident that narrower and thicker interconnect segment has a much larger Fringing Field Effect .

Pucknell et.al give the formula for fringing field capacitance for fine line metallization. It is as follows:

Where L=wire length,

t = thickness of the wire,

h = wire to substrate separation.

7.6.9.2. Interlayer capacitance.

In multi-level metallization IC Chip, interlayer capacitance becomes important therefore in area capacitance chart Table 7.6.2. we have metal 2 to metal 1 and metal 2 to polysilicon. This will occur where two level metal paths overlap or cross each other.

7.6.9.3.Inter-wire Capacitance(due to lateral field).

There is inter-wire capacitance between two metal pathways at the same level due to lateral field as shown in Figure 7.6.9.3. Along side Fringe Field Capacitance and Parallel Plate Capacitance is also shown.

7.6.9.4. Overlap Fringe Field Capacitance.

Two level metal pathways may overlap as shown in Figure 7.6.9.4. In this case Overlap Fringe-Field Capacitance is caused.This has to be ascounted for accurate modeling and simulation.

7.6.9.5. Peripheral Capacitance.

In Table 7.6.2 we have a row which gives the diffusion(active)region capacitance. These are the junction capacitance of the junction diode made by source and drain diffusion into the Well or into the substrate.

In Figure 7.6.9.5 we show the cross-section of CMOS structure achieved by N-Well Process.

We have P+ Source and P+Drain diffusion into N-Well to realize PMOS and we have N+Source and N+Drain diffusion into P-Substrate to realize NMOS. This created 12 PN Junction Diodes.

D1,D3,D4 and D6 are sidewall diodes and D2 & D5 are the bottom diodes. Table 7.6.2 in the 5th row accounts for the capacitance associated with D2 & D5 only. The side wall diodes junction capacitances are called peripheral capacitances and have not been accounted for.

Similarly N+Source and N+Drain diffusion into P-substrate have created D7,D9,D10 and D12 sidewall diodes and D8 & D11 bottom diodes. Here also 5th Row of Table 7.6.2 acounts for D8 & D11 botom diodes only.Peripheral diodes junction capacitance remain to be accounted for.

As we scale downGeneration after Generation the relative value of peripheral capacitances increases with respect to area capacitances(or bottom capacitances).

If instead of diffusion, the active regions are achieved by ion-implantation then because of the very shallow depths of the active regions the sidewall capacitances are insignificant and hence can be neglected.

Table 7.6.9.1 gives the values of the bottom junction capacitances and sidewall junction capacitances.

Table 7.6.9.1.Typical values for diffusion capacitances.

 Typical values of junction capacitances, bottom and sidewall. 5μm 2μm 1.2μm Area Capacitance(Carea) 1.0×10-4pF/μm2 1.75×10-4pF/μm2 3.75×10-4pF/μm2 Peripheral Capacitance(Cperiph) 8.0×10-4pF/μm2 Ion-implant Ion-implant

7.6.9.6. Choice of layers according to the suitability of their functions.

Metal Layers , poly-silicon layers, diffusion layers are chosen according to the functions which they are to perform.

1. VDD and Ground (VSS) should be distributed on metallic paths.
2. Long lengths of poly-silicon layer should not be used because their high sheet resistance. They are suitable only for local interconnects.
3. Capacitive effects are critical in fast signal lines. Fast signal lines should pass over interconnects with low sheet resistance and running over low permittivity dielectric layers because velocity of the signal is:

Lower is the value of relative permittivity closer is the velocity of propogation to ‘c’(velocity of light in free space)..

Table 7.6.9.2 gives the maximum length of communication lines based on the speed of

switching consideration.

Table 7.6.9.2.Electrical Rules for communication lines.

 layer Maximum legth of communication wire Lambda-based(5μm) μm-based(2μm) μm-based(1.2μm) Metal Chip wide Chip wide Chip wide Silicide 2000λ NA NA Polysilicon 200λ 400μm 250μm Diffusion(active) 20λ* 100μm 60μm

*Taking into account of peripheral and area capacitances. NA=not applicable.

Table 7.6.9.3 gives the thickness values of different layers in 0.8μm CMOS process.

Table7.6.9.3.Thickness values of different layers(0.8μm CMOS process)

 Layer Thickness(μm) Field Oxide 0.52 Gate Oxide 16nm Poly-Si thickness 0.35 Poly-Metal Oxide thickness 0.65 Metal 1 thickness 0.60 Via Oxide thickness 1.00 Metal 2 thickness 1.00 N+ junction depth 0.40 P+ junction depth 0.40 N-Well junction depth 3.5

Different terms used in Table 7.6.9.3 are explained in Figure 7.6.9.6.

In Table 7.6.9.4. we give the functional suitability of different layers.

Table 7.6.9.4.Functional suitability of different layers.

 Layer R C Comments Metal low low Use for power distribution and global signals Silicide low moderate Modest RC delay. Reasonably long wires are possible. Silicide is used in place of Poly-Si in some NMOS processes Poly-Si high moderate Moderate RC delay and high IR drop Diffusion(active) moderate high Moderate IR drop but high C hence hard to drive.

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