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SSPD_Chapter 7_Part 7_Scaling of MOS circuits_continued2

Module by: Bijay_Kumar Sharma. E-mail the author

Summary: SSPD_Chapter 7_Part 7_Scaling of MOS circuits_continued2 deals with the scaling models with constant field, constant voltage and dimensions and voltage being scaled by different scaling factors.

SSPD_Chapter 7_Part 7_Scaling of MOS circuits_continued2

7.7.7. Scaling models and scaling factors.

Figure 1
Figure 1 (Picture 1.png)

In Figure 7.7.7.1. NMOS cross-secctional view and top view are shown.

Linear dimensions both vertical and lateral are being scaled by 1/α..

DC Biasing voltage ,VDD , and Oxide thickness,D, are being scaled by 1/β.

We have three scaling models:

  1. Constant Field Scaling Model- here physical dimensions and bias voltage have the same scaling factor therefore α = β;
  2. Constant Voltage Scaling Model- here physical dimensions are scaled but bias voltage is kept constant therefore β = 1;
  3. General Scaling Model- here the two scaling factors are kept different.This is more realistic and presently widely practiced in the Industries.

7.7.7.1.Scaling Factors for Device Geometrical parameters

1. Gate Area = Ag = L×W. Each dimension is scaled by 1/α hence Ag is scaled by 1/α2.

2.Gate Capacitance per unit area = COX = ε0εOX/D where D is scaled by 1/β therefore COX is scaled by β.

3. Gate Capacitance , Cg , = COX×LW has a scaling factor of β/α2 .

4. Parasitic Capacitance, CX = ε0εSi AX/d= junction capacitance of the diode at Source-Substrate Junction and at Drain-Substrate Junction. ‘d’ is the depletion width of the diode. Since Source and Drain are at 0V and 5V respectively and substrate is also at 0V therefore depletion region around Source and Drain are d1 and d2 respectively extending primarily into P-Substrate because the two diodes are one-sided step junctions There is a depletion region d3 under the gate in the substrate. This is due to the trapped charges in the gate-oxide and due to the positive voltage a the gate electrode.

Figure 2
Figure 2 (Picture 2.png)

In Figure 7.7.7.1 cross-sectional view of NMOS structure with depletion region of ‘d’μm width is illustrated in the upper figure and in the figure below ‘d’μm’ plot with respect to Background doping of P-substrate is shown.

From Device Physics we know that for one-sided step junction:

Figure 3
Figure 3 (graphics1.png)

As the channel length is scaled down, depletion region width ‘d’ must also be scaled down to prevent the source and drain depletion regions from meeting. This is probably to prevent “Punch Through” - a phenomena which occurs in BJT also.

During scaling, cross-sectuional area AX is scaled by 1/α2 and Backgound Doping is increased so that d is scaled by 1/α.

So the scaling factor of CX is :

Figure 4
Figure 4 (graphics2.png)

Increase in substrate doping NB decreases ‘d’ but increases threshold voltage VTh which is against the required trend of scaling and hence cannot be permitted therefore substrate doping is selectively increased around Source and Drain but not under the Gate by the application of deep channel implantation.

7.7.7.2.Scaling factors for different performance parameters for General Scaling Model.

i.Carrier density in the channel = QON = COX×VGS . (since VGS = VDD hence scaling factor for VGS is the same as for VDD). Hence scaling factor for QON = β×(1/β) = 1

ii. Channel resistance RON is given as follows:

Figure 5
Figure 5 (graphics3.png)

Where ρ is resistivity of the ON channel and σ is the conductivity of the ON channel and

Figure 6
Figure 6 (graphics4.png)

Where μn = drift mobility of electrons since we are dealing with NMOS,

q= charge of an electron,

nn = number density or electron number per unit volume of the channel therefore

Figure 7
Figure 7 (graphics5.png)

Substituting Eq.7.7.2.2 and Eq 7.7.2.3 in Eq.7.7.2.1 we get:

Figure 8
Figure 8 (graphics6.png)

Therefore From Eq.7.7.2.4: RON = (L/W)×[1/(μnQON)]

Mobility is unaffected by scaling. Hence scaling factor is 1×1=1

iii Gate Delay τd = CgRON = (L×W)COX×(L/W)×[1/(μnQON)] = L2COX[1/(μnQON)]

Therefore scaling factor of Gate Delay is (1/α2)×β×1= β/α2 ;

iv Maximum toggle rate = fmax = 1/τd . Therefore the scaling factor is the reciprocal of that of Gate Delay i.e. (α2 /β) .

v Saturation Current IDSS = (μnCOX/2)(W/L)(VGS-Vth)2 Here both VGS and Vth are being scaled by (1/β). Hence the scaling factor is β×1×(1/β)2=1/β.

vi. Switching energy per gate Egate = (1/2)Cg(VDD)2. The scaling factor is (β/α2)(1/β)2=

1/(α2β).

vii. Power dissipation per gate Pgate = Quiescent Power + Dynamic Power

= (VDD)2/RON + fmax×Egate . Hence the scaling factor is (1/β)2×1+(α2/β)×(1/(α2β)

=1/β2.

viii. Power dissipation per unit area = P□= Pgate/Agate . Therefore the scaling factor = (1/β2)/(1/α2) = (α/β)2 .

ix. Power Speed Product is the Figure of Merit of the Gate = Pgate× τd . This has a scaling factor = 1/β2× β/α2=1/(βα2).

Table 7.7.7.2.1. Scaling factors for different performance parameters for General Scaling Model.

Table 1
Performance parameter Formula Scaling Factor
QON COX×VGS 1
RON (L/W)×[1/(μnQON)] 1
τd CgRON = L2COX[1/(μnQON)] β/α2
Maximum toggle rate fmax = 1/τd (α2 /β)
IDSS (μnCOX/2)(W/L)(VGS-Vth)2 1/β
JDSS IDSS/(L×W) α2 /β
Egate (1/2)Cg(VDD)2 1/(α2β)
Pgate (VDD)2/RON +fmax×Egate 1/β2
P□ Pgate/Agate (α/β)2
Figure of Merit Pgate× τd 1/(βα2)

7.7.7.3. Scaling factors for all the three scaling models.

In this section we will tabulate the scaling factors for all the three scaling models namely:

  1. Constant Electric Field Model also known as Full Scaling Model. Here α=β.
  2. Constant Voltage Model also known as Fixed Voltage Model. Here β =1.
  3. General Scaling Model. Here two scaling factors are kept different. This is most realistic and generally accepted by Industries.

Table 7.7.7.3.1. Scaling Factors for long channel devices for the three scaling models.

Table 2
Parameter   Full Scaling General Scaling Fixed Scaling
W,L,D   1/α 1/ α for W&L, 1/β for D 1/ α
VDD , Vth   1/ α 1/β 1
NB* V/d2 α α 2/β α 2
Area/device WL 1/ α2 1/ α2 1/ α2
COX = C□g 1/D α β 1
Cg COXWL 1/α β/ α2 1/ α2
kn or kp COXW/L α β 1
IDSS kV2 1/ α 1/β 1
td CgV/ IDSS 1/ α β/ α2 1/ α2
Pgate CgV2/td 1/ α2 1/β2 1
Egate CgV2 1 α3 1/(β α2) 1/ α2

*From Eq.7.7.7.1.1 :

Figure 9
Figure 9 (graphics7.png)

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